IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 2, FEBRUARY 2019 403 A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS Jorge Lagos , Student Member, IEEE, Benjamin Hershberg , Member, IEEE, Ewout Martens , Member, IEEE, Piet Wambacq , Senior Member, IEEE , and Jan Craninckx , Fellow, IEEE Abstract— Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introduc- ing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring amplifier (ringamp) to achieve both high speed and linearity in low-voltage nanoscale CMOS designs. A tunable ringamp biasing scheme using an anti-parallel arrangement of CMOS transistors and an active ringamp-based common-mode feedback are also introduced. A single-channel prototype ADC is implemented in a standard 28-nm CMOS process, achieving 58.7-dB SNDR and 72.4-dB SFDR at 600 MS/s while consuming 14.5 mW from a single 0.9-V supply, resulting in Walden and Schreier figure-of-merit (FoM) values of 34.4 fJ/conv.-step and 161.9 dB, respectively. Index Terms— Active common-mode feedback (CMFB), gain calibration, pipelined ADC, ring amplifier (ringamp), single channel. I. I NTRODUCTION T HE ever-increasing demand for higher data throughput that pushes the boundary of ADC performance has fueled the development of converters that seek to simultaneously maximize both linearity and bandwidth (BW). Typical appli- cations that benefit from such ADCs include software-defined radios, cellular base stations, satellite and radar receivers, cable TV set-top units, and instrumentation equipment. The adoption of wide-BW, high-speed data converters in these applications provides benefits not only in terms of system complexity reduction but also in terms of reconfigurability, encouraged by the availability of cheap digital processing power in deeply scaled CMOS processes. ADCs targeting the above requirements often rely heav- ily on the use of time interleaving (TI) and digital calibration [1]–[9]. These techniques are used to overcome the intrinsic speed and linearity limits of the technology and Manuscript received March 15, 2018; revised June 17, 2018 and September 18, 2018; accepted October 24, 2018. Date of publication November 28, 2018; date of current version January 25, 2019. This paper was approved by Associate Editor Jeffrey Gealow. (Corresponding author: Jorge Lagos.) J. Lagos and P. Wambacq are with imec, 3001 Leuven, Belgium, and also with the Department of Electronics and Informatics (ETRO), Vrije Universiteit Brussel, 1050 Brussels, Belgium (e-mail: jorge.lagosbenites@imec.be). B. Hershberg, E. Martens, and J. Craninckx are with imec, 3001 Leuven, Belgium. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2018.2879923 Fig. 1. Effective number of bits versus BW for ADCs with more than 9 ENOB (Nyquist input) published at ISSCC and VLSI conferences from 1997 to 2018 [11]. Unfilled symbols denote the TI systems. to correct the artifacts arising from TI itself [10]. However, since the complexity of TI calibration grows rapidly with the number of interleaved channels, the maximization of the per-channel speed becomes of paramount importance for the implementation of ADCs with high linearity and BW. As shown in Fig. 1 [11], most ADCs reported to date with greater that 9 ENOB and higher than 400 MS/s employ TI, while only a handful reaches this performance region with a single channel. The power efficiency of those fast single-channel solutions, as typically expressed by their Schreier and Walden figure-of-merit (FoM) values, is, how- ever, not particularly high. Inspired by these observations, this paper proposes an alternative approach for pushing the per-channel performance into this region while attaining improved power efficiency. Within the realm of high linearity and BW ADCs, 1 the fastest channel architecture tends to be some form of pipelin- ing with a low number of bits per stage. The attainable power efficiency of such designs is usually limited by the amplifiers needed for the residue amplification at each stage. The classical and still predominant approach to residue gen- eration is closed-loop (CL) amplification with operational transconductance amplifiers (OTAs), which are limited by their high power consumption and poor scaling properties [1], [3], [5], [8], [12]–[14]. In the high-speed designs, multi- stage Miller-compensated amplifiers are too slow, and highly cascoded single-stage topologies using special high-voltage 1 In the remainder of this paper, we denote by high-linearity, high-BW converters those achieving ≥400 MS/s and ≥9 ENOB with a Nyquist input. 0018-9200 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.