FPGA Based Synchronous Multi-Port SRAM Architecture for Motion Estimation Purnachand Nalluri 1,2 , Luis Nero Alves 1,2 , Antonio Navarro 1,2 1 Institudo de Telecomunicações, Pólo-Aveiro, Campus Universitário de Santiago, 3810-193 Aveiro, Portugal. 2 Departamento de Electrónica, Telecomunicações e Informática, Universidade de Aveiro Campus Universitário de Santiago 3810-193 Aveiro, Portugal. nalluri@av.it.pt , nero@ua.pt , navarro@ua.pt . Abstract Very often in signal and video processing applications, there is a strong demand for accessing the same memory location through multiple read ports. For video processing applications like Motion Estimation (ME), the same pixel, as part of the search window, is used in many calculations of SAD (Sum of Absolute Differences). In a design for such applications, there is a trade-off between number of effective gates used and the maximum operating frequency. Particularly, in FPGAs, the existing block RAMs do not support multiple port access and the replication of DRAM (Distributed RAM) leads to significant increase in the number of used CLBs (Configurable Logic Blocks). The present paper analyses different approaches that were previously used to solve this problem (same location reading) and proposes an effective solution by using an efficient combinational logic to synchronously and simultaneously read the video pixel memory data through multiple read-ports. 1. Introduction With the increased demand for multi-tasking and parallel processing, the modern applications for FPGA and ASIC based memory architectures cannot rely just on single port or dual port memories. The only possible solution for this is to increase the bus bandwidth and implement multiple port memories. Especially when considering synchronous memories, implementing multiple read port memory operation is required [1-2]. There are many applications where multiple read operations are highly required. For example, in robotic vision system, the object recognition system has to search many samples of live video frames and output one object that has minimum error. In reconfigurable vision systems, a shared memory is necessary to access the video content through multiple resources [1-2]. Similarly, in video compressions system, a shared memory is required to process many samples of video frame blocks in one clock cycle. The present paper focuses on the key role of multi-port SRAM (Static RAM) in motion estimation [3] application. Section 2 explains the memory architecture requirement in motion estimation. Section 3 compares the performance of some architectural solutions. Section 4 proposes a new architecture suited for FPGAs. Section 5 details Fig. 1(a). Illustration of ME Process To next Processing blocks Control Unit From External Memory Large Data width internal port Local Memory Unit Control Signals from external master SAD Computation Unit Fig. 1(b). Architecture for real time processing of Motion-Estimation