www.ijecs.in International Journal Of Engineering And Computer Science ISSN:2319-7242 Volume 6 Issue 6 June 2017, Page No. 21870-21874 Index Copernicus value (2015): 58.10 DOI: 10.18535/ijecs/v6i6.53 Chiranjeet Kumar, IJECS Volume 6 Issue 6 June, 2017 Page No. 21870-21874 Page 21870 A Design of AMBA AXI4-Lite ACE Interconnect Protocol for Transaction- based SoC Design Techniques Integration Chiranjeet Kumar 1 Dr. M. Gurunadha Babu 2 1 M.Tech, Department of VLSI system design 2 M.Tech, Ph.D., Head of the Department (ECE) CMR Institute of Technology, Medchal Road, Hyderabad, Telangana 501401-India chiranjeet9650530563@gamil.com 1 mgurunadhababu@gmail.com 2 Abstract-- The chip design in the 21 st century has undergone various changes due to the increased customer demands and this lead to design complexity in systems-on-chip (SoC), network-on-chip (NoC), application-specific integrated circuit (ASIC), and field-programmable gate array (FPGA) designs. This creates a situation to develop an advanced system to resolve the complexity issue in meantime. The verification step consumes the major portion of the VDHL time and transaction-level modeling (TLM) and Bus Functional modeling (BFM) are used in order to reduce this effort. Transaction-level modeling (TLM) is a technique used to describe the system by using the standard function calls which defines all the transactions which are required to verify the functionality of the system at the architecture level. The usage of the transaction based techniques are designed for the software analysis and for the first time, in this research work it is used for the physical hardware design and its analysis based on the AMBA ace-lite architecture. In past AMBA AXI4 Bus Interconnects is used for the hardware system design but it fails to meet the practical design requirements and the proposed AMBA ace-lite architecture has yielded the desired results with low complexity. With the proposed AMBA ace-lite architectural design for hardware system design, several SoC/NoC subsystems can easily be interconnected in basically the same manner as how transaction-based simulation models are being written. The proposed methodology is useful for the hardware design engineers to deal with the complexity simplification issues by bringing the benefits of transaction-based verification (TBV) to it approach. Index Terms: Transaction Level modeling (TLM), Advanced Extensible interface (AXI), Advanced Micro Controller Bus Architecture (AMBA), FPGA, Software, Hardware 1. Introduction To meet the customer demands and the time to market always designers and the verification engineers look for methods which can reduce the effort as well as the time. Adopting Transaction-level modeling (TLM) technique and developing intellectual properties (IP) and flexible automated tools for design as well as verification are some of the methods which are targeted towards the same. In the early days as each chip manufacture had their own bus, standardization of the bus become necessary to enable the reusability of the intellectual properties (IP).Many manufacturer developed standard busses among which some of them become very popular due to their performance, hierarchy and the advanced features. Standard busses which become very popular are Advanced Micro Controller Bus Architecture (AMBA) from ARM, CORE CONNECT from IBM. Using these standards interconnects not only enables intellectual properties (IP) reusability, provides flexibility, compatibility. These interconnects have multi-layer architecture. Between masters and slaves it can be used as a crossbar switch. Developing and verifying these interconnects or the busses become important. Because of the availability of wide variety of intellectual properties (IP) from ARM and advanced intellectual properties (IP) from third party vendors for Advanced Micro Controller Bus Architecture (AMBA) bus, this is more popular than others. There are various versions of Advanced Micro Controller Bus Architecture (AMBA) from AMBA1.0 to AMBA 5.0. On the other end of the design flow, a pure logic simulation can take place at the register transfer level (RTL). In a conventional SoC logic simulation, RTL models written in hardware description language (HDL) such as VHDL and Verilog are employed as the system hardware. If a processor model is necessary, a design sign-off model (DSM) will typically be used. The advantage of the logic simulation is evidently its great fidelity to the real implementation, i.e. accurate SoC functional and performance analysis. This is nonetheless a price too expensive to pay in terms of the lengthy simulation time. The time consumption has actually further worsened lately due to the high SoC complexity that requires a longer RTL development phase. Moreover, a pure logic simulation cannot execute any software in a reasonable amount of time. A system can only integrate its associated software for observation and analysis rather late in the