2156 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 10, OCTOBER 2006 Voltage-Aware Static Timing Analysis Dionysios Kouroussis, Member, IEEE, Rubil Ahmadi, Member, IEEE, and Farid N. Najm, Fellow, IEEE Abstract—Static timing analysis (STA) techniques allow a de- signer to check the timing of a circuit at different process corners, which typically include corner values of the supply voltages as well. Traditionally, however, this analysis only considers cases where the supplies are either all low or all high. As will be dem- onstrated, this may not yield the true maximum delay of a circuit because it neglects the possible mismatch between the supplies of successive gates on a path. A new methodology for timing analysis is proposed, where, in a first step, the critical paths of a circuit are identified under an assumption that all the supply nodes are independent of one another, thus allowing for mismatch between the supplies. Then, given these critical paths, the authors incorpo- rate into the analysis the relationships between the supply node voltages by considering the power grid that they are tied to, and refine the worst case time delay values on a per-critical-path basis. This refinement is posed as a sequence of optimization problems where the operation of the circuit is abstracted in terms of current constraints. The authors present their technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids. Index Terms—Power grid, rail voltage variations, static timing analysis, verification tools. I. I NTRODUCTION D UE to the reduction in supply voltages, resulting from technology scaling, the timing of modern integrated cir- cuits has become highly sensitive to supply voltage fluctuations. Thus, in the analysis and verification of high-performance chips, it is essential that static timing analysis (STA) takes into account power supply variations. Traditionally, this has been done by performing STA with a setting of the supply voltages that results in worst case delay for each gate on the path under study. However, we have found that using worst case gate delays in the context of traditional STA does not necessarily yield the worst case path delay. This is due to the fact that mismatch between the supply settings of successive gates on a path turns out to have a bigger effect on the worst case path delay, as we will show. Therefore, it emerges that one really has to consider the voltages on the power supply grid and consider what their worst case arrangements are and what the corresponding worst case delay is. In other words, it is not Manuscript received October 29, 2004; revised February 8, 2005 and June 30, 2005. This work was supported in part by Micronet, by ATI Tech- nologies, by Altera Corporation, and by the Semiconductor Research Corpo- ration (SRC) under Contract 2003-TJ-1070. This paper was recommended by Associate Editor S. Sapatnekar. D. Kouroussis and F. N. Najm are with the Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON M5S 2E4, Canada (e-mail: diony@eecg.utoronto.ca). R. Ahmadi was with the Department of Electrical and Computer Engineer- ing, University of Toronto, Toronto, ON M5S 2E4, Canada. He is now with ATI Technologies, Toronto, ON M5K 1B2, Canada. Digital Object Identifier 10.1109/TCAD.2005.860953 enough to work with local worst case gate delays, one must look more globally at the whole path delay and consider how it depends on the voltages on the grid. To address this problem, we are developing a framework for timing analysis that looks for worst case delay, taking into account supply voltage variations. A key part of the solution requires one to capture exactly how the “power tap” voltages (nodes where individual gates or cells draw their current from the power supply network) are related, if any. These node voltages are not independent of one another due to the fact that the power taps are all part of the on-chip power/ground network (simply, the power grid). Thus, the structure and the currents in the power grid become part of the overall problem of chip timing verification. Our framework is in two phases. In a first phase, we apply an STA approach that assumes that all the power taps have voltages that are completely independent of one another. This technique will be described in Section III, a preliminary version of which has appeared in [1]. This technique allows for two successive gates on a path to have a big mismatch between their supplies, and is clearly not realistic for all gates (although it may be real- istic for some cases). Nevertheless, as a result of this first-phase STA, we know the absolute worst case delay for the circuit and we have a list of the critical paths. In the second phase of our approach, we take into account the presence of the power grid and operate on the list of critical paths resulting from the first-phase STA. For each path, we re- duce its delay estimate, making it more realistic. This corrective action is applied to every critical path, starting with the one with the largest delay, until a path is reached whose corrected delay is larger than the uncorrected delay of the next path on the original list. When this happens, the path in hand has the worst case delay for this circuit and the analysis is complete. The corrective action applied to each path must somehow take into account the currents and voltages on the power grid in order to discover the relationships among the power tap node voltages on that path. This is a very difficult problem because of the wide range of behaviors that the power grid can exhibit. The grid captures the exact relationship between the power tap nodes via the dynamical system equations that represent the grid. Most techniques for power grid analysis use some form of circuit simulation to compute the voltage fluctua- tions. However, given the very large number of possible circuit behaviors, one needs to simulate the circuit (for the currents) and the grid (for the voltage drops) for a large number of clock cycles or vector sequences, which is impractical. Add to this the fact that modern grids are huge, and it becomes clear that this straightforward simulation-based approach is prohibitively expensive. As an alternative, we will describe a “vectorless” 0278-0070/$20.00 © 2006 IEEE