3510 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors Renan Doria Trevisoli, Rodrigo Trevisoli Doria, Michelly de Souza, Member, IEEE, Samaresh Das, Isabelle Ferain, and Marcelo Antonio Pavanello, Senior Member, IEEE Abstract—This paper proposes a drain current model for triple- gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its deriva- tives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short-channel devices down to 30 nm at different temperatures have been also used to validate the model. Index Terms—Drain current model, junctionless nanowire transistors (JNTs), short-channel effects (SCEs), temperature dependence. I. I NTRODUCTION S CALING MOS planar transistors becomes a challenging task for devices with reduced channel length (L) due to the loss of the electrostatic control of the charges in the channel. This loss is related to the depletion regions of the source/channel and drain/channel p-n junctions, which starts controlling part of the channel charges. In order to provide better electrostatic control, multiple-gate devices have been introduced [1]–[6], enhancing the performance of short-channel devices in comparison to single-gate ones. Therefore, these devices are considered as promising for sub-20-nm era. Gen- erally, all devices are based on the use of semiconductor p-n junctions. For inversion-mode (IM) field-effect transistors (FETs) with a channel length of interest for the present and Manuscript received August 2, 2012; accepted September 4, 2012. Date of publication October 12, 2012; date of current version November 16, 2012. This work was supported in part by CAPES, by FAPESP, and by CNPq (all are Brazilian research-funding agencies). The review of this paper was arranged by Editor K. Roy. R. D. Trevisoli is with the University of São Paulo, São Paulo 05508-900, Brazil (e-mail: renantd@lsi.usp.br). R. T. Doria, M. de Souza, and M. A. Pavanello are with Centro Universitário da FEI, São Bernardo do Campo 09850-901, Brazil (e-mail: rtdoria@fei.edu.br; michelly@fei.edu.br; pavanello@fei.edu.br). S. Das is with Tyndall National Institute, Cork, Ireland (e-mail: samaresh.das@tyndall.ie). I. Ferain is with Globalfoundries, Malta, NY 12020 USA (e-mail: isabelle.ferain@gmail.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2012.2219055 Fig. 1. (a) Schematic 3-D view and (b) longitudinal section of a triple-gate n-type JNT. future technology nodes, sharply defined junctions between the source/drain regions and the channel are needed. Therefore, ultrafast annealing methods and the development of novel dop- ing techniques are being investigated. In order to avoid the use of such expensive techniques, junctionless nanowire transistors (JNTs), also called gated resistors and pinchoff FETs, have been proposed [7]–[11]. JNTs are shown to provide superior control of short-channel effects (SCEs) as compared to their IM counterparts [12]. Junctionless devices are silicon nanowires which present a heavy and constant doping concentration from the source to the drain, such that there are no junctions or doping gradients. JNTs are multiple-gate devices, with their gate stack wrapped around the nanowire. It is worth mentioning that an n-type dopant (with concentration N D ) is used for nMOS devices whereas a p-type dopant (with concentration N A ) is used for pMOS ones. Fig. 1(a) shows a schematic view of a triple-gate JNT, where the gate and buried oxide thicknesses (t ox and t Box , respectively), the channel length, and the nanowire width (W ) and height (H) are indicated. In Fig. 1(b), the longitudinal section of an n-type JNT is shown, where a uniform doping profile is exhibited. JNTs work in a way similar to that in accumulation-mode SOI (AMSOI) MOSFETs [13]. In the subthreshold operation, the silicon nanowire is fully depleted due to the gate material work function difference, such that carriers can only flow through diffusion, presenting an exponential dependence of the drain current (I D ) with the gate voltage (V G ) variation. When a portion of the channel is no longer depleted, bulk current flows through a neutral path. The gate voltage at which the device starts to leave the fully depleted regime is defined as the threshold voltage (V TH ). As V G is increased above the threshold voltage, the width of the depletion region decreases, increasing both the width of the neutral path in the center of the nanowire and the magnitude of the bulk current. When the gate 0018-9383/$31.00 © 2012 IEEE