Methodology for Application-Dependent Degradation Analysis of Memory Timing Dani¨ el Kraak Innocent Agbo Mottaqiallah Taouil Said Hamdioui Delft University of Technology Mekelweg 4, 2628 CD Delft, The Netherlands {D.H.P.Kraak, I.O.Agbo, M.Taouil, S.Hamdioui}@tudelft.nl Pieter Weckx 1,2 Stefan Cosemans 1 Francky Catthoor 1,2 1 imec vzw., Kapeldreef 75, B-3001, Leuven, Belgium 2 Katholieke Universiteit Leuven, ESAT, Belgium {Pieter.Weckx, Francky.Catthoor}@imec.be Abstract—Memory designs typically contain design margins to compensate for aging. As aging impact becomes more severe with technology scaling, it is crucial to accurately predict such impact to prevent overestimation or underestimation of the margins. This paper proposes a methodology to accurately and efficiently analyze the impact of aging on the memory’s digital logic (e.g., timing circuit and address decoder) while considering realistic workloads extracted from applications. To demonstrate the su- periority of the methodology, we analyzed the degradation of the L1 data and instruction caches for an ARM v8-a processor using both our methodology as well as the state-of-the-art methods. The results show that the existing methods may significantly over- or underestimate the impact (e.g., the decoder margin up to 221% and the access time up to 20%) as compared with the proposed scheme. In addition, the results show that in general the instruction cache has the highest degradation. For example, its access time degrades up to 9% and its decoder margin up to 44%. Index Terms—Memory, Aging, Timing, Address Decoder I. I NTRODUCTION The continuous downscaling of CMOS technology has resulted in significantly improved performance and func- tionality of Integrated Circuits (ICs). However, downscaling worsens the reliability due to the increased time-zero and time-dependent variabilities [1]. Time-zero variability, often referred to as process variation, is caused by imperfections during production. As a result, fabricated ICs have deviating performance. Time-dependent variability is caused by oper- ational stress during the lifetime of the ICs. They include environmental variations, such as voltage and temperature fluctuations, and aging variations due to, for instance, Bias Temperature Instability (BTI) [2]. To achieve a high quality product in terms of low failure rates at optimal design, it is essential to estimate the impact of these variabilities. In this work, we focus on the degradation of SRAMs. They often dominate the total area of SoCs and microprocressors and, therefore, their area, power, and performance are very optimized. Hence, it is crucial to estimate their degradation. Previous studies on SRAM reliability have mainly focused on estimating the impact of aging on single memory compo- nents (e.g., memory cells). The majority of these works inves- tigated the degradation of the memory cell array [3–7], while fewer works investigated the impact on the peripheral circuitry, such as the sense amplifier [8]. Limited work investigated the impact of aging while considering multiple components [9] or This work was supported through the project TRACE (CATRENE, Grant 16ES0488K-16ES0502, 16ES0737) and PRYSTINE (ECSEL, Grant 783190). the complete memory core [10, 11]. The latter provides a more accurate estimation, since they also include the impact of the interaction between the aged components. Nevertheless, the digital logic, such as the timing circuit and address decoder, have received little attention. To the best of our knowledge only two works included the digital circuitry in their anal- ysis [10, 11]. They examine metrics such as the access time (which is dominated by the digital circuit) and decoder margin. However, only a single path of the memory was analyzed to estimate the impact based on simplified artificial workloads. For example, the authors in [11] assume that each address is accessed an equal amount of times, while in [10] the authors assume that all operations are spread over only four addresses. These regular workloads do not reflect the reality; hence, they may lead to inaccurate results. Real applications access the memory in a much less regular pattern, as is shown in this work. Therefore, the logic paths receive different stresses and they all need to be analyzed to get a good estimation of the impact on metrics such as the access time and decoder margin. To address these shortcomings, this work proposes a methodology to efficiently and accurately analyze the impact of aging on the digital logic (e.g., timing circuit, address decoder) of memories using real applications. This method- ology is based on performing static timing analysis. Using this methodology it becomes feasible to efficiently analyze all digital logic paths, such as the ones related to the access time and decoder margin. In short, the contributions of this work are as follows: 1) It proposes a methodology to analyze the impact of real applications on the memory’s digital logic. 2) It investigates the accuracy of the proposed method based on real applications versus artificial workloads used in the state-of-the-art. 3) As a case study, it investigates and compares the impact of aging due to real applications on the L1 data and instruction caches of an ARM v8-a processor. 4) All the above work is performed using an industrial- strength 14 nm FinFET SRAM design and an accurate aging model. The outline of this paper is as follows: Section II provides the background. Section III presents the proposed methodol- ogy. Sections IV discusses the performed experiments and the obtained results. Section V contains a brief discussion. Finally, Section VI concludes this work. 162 978-3-9819263-2-3/DATE19/ c 2019 EDAA