Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications A. Srivastava a, * , Partha Sarkar b , Chandan Kumar Sarkar c a Electrical and Electronics Engineering Department, BITS, Pilani, Rajasthan 333031, India b Department of Electronics and Communication Engineering, Gandhi Institute of Technology and Management, Bhubaneswar, Orissa, India c Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, India article info Article history: Received 19 September 2008 Received in revised form 11 November 2008 Available online 8 February 2009 abstract The impact of high permittivity gate dielectrics with different equivalent oxide thickness (EOT) for con- ventional, low and high tilt angle halo implants on the performance of 100 nm n-MOSFETs device is stud- ied using device simulator Synopsys ISE-TCAD. In this paper, we systematically increase the value of gate dielectric (3.9–50) and investigate its effects on conventional, low angle of tilt (10 o ) and high angle of tilt (50 o ) halo implants for different device parameters of 100 nm n-MOSFETs using two different EOT viz. 1.5 nm and 2.0 nm. The impact of gate dielectric permittivity along with the different angles of halo implants on short channel performance contributing to the DIBL, the subthreshold swing, I ON /I OFF ratio, and the threshold voltage V T are studied for two different EOT thicknesses. The device has been investi- gated for digital performance parameters like the variation of substrate–body voltage on DIBL, I OFF , I ON and the threshold voltage V T for sub 100 nm technology generation. It has also been investigated for ana- log performance like trans-conductance generation factor (gm/I D ) and overall gain (gmR 0 ). Ó 2008 Elsevier Ltd. All rights reserved. 1. Introduction According to the ITRS roadmap, CMOS with gate length below 100 nm will require an oxide thickness of less than 2.0 nm, which corresponds to just few layers of silicon dioxide atoms. With such an ultra thin gate oxide, direct tunneling occurs resulting in an exponential increase of gate leakage current [1–5]. The increase in gate leakage current will increase the power dissipation leading to deterioration of the device performance and the circuit stability for ULSI circuits. High-k gate dielectrics such as Al 2 O 3 , ZrO 2 , La 2 O 3 and HfO 2 have received a lot of attention recently to prevent direct gate tunneling [6–8]. Infact, HfO 2 based materials have been recog- nized as the most promising gate dielectric material [6]. Recently, sufficient work has been done to understand the properties of high-k gate dielectrics including the technological issues with their fabrication. Some of the problems currently being looked at by var- ious research groups include interfacial layer formation during the thermal process, micro-crystal formation during the process and the mobility degradation [1,2]. Also, for the higher physical gate dielectric thickness with (by a factor of k gate /k SiO2 ) high k gate , MOS transistors results in weakening of the gate control [9,10], which leads to poor sub threshold performance and increased short channel effects. Conventional (CON) bulk MOSFET devices have been the main- stream of ULSI technology for the past two decades. It is a great challenge to scale the devices below 100 nm due to the severe short channel effects, including the roll-off of threshold voltage, the increase of the leakage currents, and increase in the sub- threshold swing. To suppress the short channel effects in sub- 100 nm region, the lateral channel engineering was proposed in which the high doping concentration was realized locally through the halo or the pocket implants. The implant can be either sym- metrical or asymmetrical with respect to source or drain. It was re- ported that the threshold voltage roll-off and the sub threshold leakage current could be reduced by such implants next to the source/drain (S/D) junction [11,12]. Reduction of short channel ef- fects has also been reported through large angle tilt implant in asymmetric halo structures [13]. In this paper we systematically investigate the effects of con- ventional, low and high tilt angle halo implants with different high-k gate dielectric materials using two different EOT for deter- mining different device parameters of 100 nm lateral asymmetric channel (LAC) MOSFETs. The effective channel length (L eff ) have been about 70 nm with large angle tilt implant. Device perfor- mance parameters, for analog and digital circuits like current-volt- age characteristics (I D vs. V D and I D vs. V G ), sub-threshold characteristics, threshold voltage, I ON /I OFF ratio and DIBL has been 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.11.008 * Corresponding author. E-mail addresses: asrivastava@bits-pilani.ac.in (A. Srivastava), partha_sar- kar_9@yahoo.com (P. Sarkar), phyhod@yahoo.co.in (C.K. Sarkar). Microelectronics Reliability 49 (2009) 365–370 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel