Capacitance estimation for InAs Tunnel FETs by means of full-quantum k  p simulation E. Gnani ⇑ , E. Baravelli, A. Gnudi, S. Reggiani, G. Baccarani ARCES and DEI, University of Bologna, Viale del Risorgimento 2, 40136 Bologna, Italy article info Article history: Available online 16 January 2015 The review of this paper was arranged by B. Gunnar Malm Keywords: Full-quantum simulation Parasitic capacitance Tunnel Field-Fffect Transistor (TFET) abstract We report for the first time a quantum mechanical simulation study of gate capacitance components in aggressively scaled InAs Nanowire Tunnel Field-Effect Transistors. It will be shown that the gate-drain capacitance exhibits the same functional dependence over the whole V gs range as the total gate capaci- tance, albeit with smaller values. However, as opposed to the previous capacitance estimations provided by semiclassical TCAD tools, we find that the gate capacitance exhibits a non-monotonic behavior vs. gate voltage, with plateaus and bumps related with energy quantization and subband formation determined by the device cross-sectional size, as well as with the position of channel-conduction subbands relative to the Fermi level in the drain contact. From this point of view, semiclassical TCAD tools seem to be inac- curate for capacitance estimation in aggressively-scaled TFET devices. Ó 2015 Elsevier Ltd. All rights reserved. 1. Introduction Novel device concepts are being widely studied to overcome scaling limitations of traditional planar bulk CMOS technologies, such as short-channel effects and leakage currents. One major issue with conventional MOSFETs is that carrier injection at the MOSFET source-channel junction is bound by the exponential tail of Fermi statistics because it is governed by thermionic emission over a potential barrier [1]. This implies that the MOSFET inverse subthreshold slope (SS) cannot be reduced below 60 mV/decade at room temperature [2]. However, power-dissipation increase in next-generation digital systems must be contrasted by reducing the voltage supply V DD . To this purpose, transistors with SS ’ 45 mV/decade or lower, on at least three decades of drain current I ds , should be designed [3]. A possible candidate to replace conventional CMOS is the Tunnel FET (TFET) [4,5], which is expected to provide very steep subthreshold slopes and, thus, reduced supply voltages, while retaining full compatibility with CMOS technology. The TFET struc- tural similarity with standard MOSFETs makes it possible to take advantage from the evolution of CMOS technology, allowing for both horizontal and vertical implementations with double-gate (DG) and gate-all-around (GAA) configurations. Besides, the use of intrinsic channels promises reduced random-dopant induced variability. Current challenges to mainstream introduction of the TFET technology include the difficulty to achieve sufficiently high on-state currents. However, merely increasing I on does not neces- sarily result in a better TFET-based circuit performance [6]. Standard performance metrics for digital circuits are propaga- tion delay and power dissipation. The device properties affecting the aforementioned parameters are the drive current in saturation and linear regions, the gate and Miller capacitances, and the output conductance. Hence, a detailed understanding of TFET capacitances is essential for the design of TFET-based circuits [7]. It was shown in [8] that the partitioning of the total gate capacitance C gg in a TFET is significantly different from that in a MOSFET, fundamentally due to the difference in inversion charge distribution. For a MOSFET oper- ating in the linear region, both source and drain (S/D) regions are connected to the channel, and C gg is evenly split into source and drain contributions: C gd ’ C gs ’ C gg =2, with C gs the gate-source and C gd the gate-drain capacitances, respectively. In saturation, C gs ’ 2=3 C gg , and C gd ’ 0. For a TFET, instead, the drain is connected to the channel both in linear and saturation regions. C gd and C gs are thus unequal, with C gd representing a larger fraction of C gg . To our knowledge, the calculation of TFET parasitic capacitances has only been carried out with semiclassical TCAD tools so far [8]. The accuracy of such tools may be questionable when aggressively- scaled devices are investigated. In contrast with the majority of published papers, a full-band quantum simulation approach is used in this work to properly account for quantum effects, which strongly influence TFET devices, and the dependence of C gg ; C gd http://dx.doi.org/10.1016/j.sse.2014.12.005 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved. ⇑ Corresponding author. Tel.: +39 051 209 3773; fax: +39 051 209 3779. E-mail addresses: elena.gnani@unibo.it (E. Gnani), emanuele.baravelli@unibo. it (E. Baravelli), antonio.gnudi@unibo.it (A. Gnudi), susanna.reggiani@unibo.it (S. Reggiani), giorgio.baccarani@unibo.it (G. Baccarani). Solid-State Electronics 108 (2015) 104–109 Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse