International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-1, November 2019 4763 Published By: Blue Eyes Intelligence Engineering & Sciences Publication Retrieval Number: A4588119119/2019©BEIESP DOI: 10.35940/ijitee.A4588.119119 Abstract: The need for miniaturization has been the driving force in chip manufacturing. The proliferation of IoT, robotics, consumer electronics and medical instruments pose unprecedented demands on the embedded system design. The area optimization can be achieved either by reducing the size of transistors or by optimizing (reducing) the circuit at the gate level. The first solution has attracted many researchers while the later has not been explored to its full potential. The aim is to design a System on Chip (SoC) to satisfy the dynamic requirements of disruptive technologies while occupying the lesser area. The design and testing of communication interfaces such as Serial Peripheral Interface (SPI), Inter-IC Communication (I2C), Universal Asynchronous Receiver and Transmitter (UART) are very crucial in the area optimization of microcontroller design. Since SPI being an important communication protocol, this work reports the preliminary research carried in the design and verification of it. In this work, Verilog is used for the design and verification of the SPI module. The results show that there is a drastic reduction in the number of Look-Up-Tables (LUTs) and slices required to build the circuit. We conclude that sophisticated optimization techniques of the circuit at the gate level has the potential to reduce the area by half. Keywords: Area Optimization, Communication Protocol, Serial Peripheral Interface, Structural Modeling. I. INTRODUCTION The ever-increasing proliferation of IoT devices has posed demand on processing devices (can be of 5 different categories namely Microprocessor, Microcontroller, Digital Signal Processor, Field Programmable Gate Array, Application Specific Integrated Circuits) to accommodate the varied type of peripheral devices such as sensors and actuators [1] and [2]. Though microcontrollers are less power hungry and work with lower clock frequency their massive adoption in the automation industry can be owed to their ability to interface (to a peripheral device) with minimal hardware resources. The presence of various modules (Analog-to-Digital Converter, memories, communication modules, timers/counters, Digital-to-Analog Converter, etc.) within the microcontroller will subdue the need to have additional hardware for interfacing [3], [4] and [5]. A typical Revised Manuscript Received on November 08, 2019 * Correspondence Author Amrut Anilrao Purohit*, Research Scholar, Department of Electronics and Communication Engineering, VTU, Belagavi, India. Assistant Professor, School of Electronics and Communication Engineering, REVA University, Kattigenahalli, Yelahanka, Bengaluru, KTK India-560064. Mohammed Riyaz Ahmed, and R Venkata Siva Reddy, are with School of Electronics and Communication Engineering, REVA University, Kattigenahalli, Yelahanka, Bengaluru, KTK India-560064. master-slave arrangement between a microcontroller and peripheral device is depicted in Fig.1. Fig. 1. Microcontroller with various peripherals including SPI, I2C, UART Designing an efficient communication protocol which governs the communication between the processing device and the peripheral(s) is the crux of the matter. The seamless communication happens either in the synchronous (master-slave) fashion or asynchronous fashion. Serial Peripheral Interface (SPI), Inter-IC Communication (I2C), and Universal Asynchronous Receive Transmit (UART) are quite a bit slower than protocols like Universal Serial Bus (USB), Ethernet, Bluetooth, and Wi-Fi, but they are a lot simpler and manage with less hardware and system resources [6] and [7]. For low-data rates, SPI, I2C, and UART are ideal for communication between microcontrollers or microcontroller and sensors/actuators [8], [9] and [10]. Fig. 2. Trends graph showing the dominance of SPI among all interface communication protocols: A comparison since 2004, obtained from Google trends. SPI has been investigated either for reducing the power consumption or for increasing the speed. One more domain which has got equal attention is of area reduction. Though many approaches have been reported to date, structural modeling remains unexplored [11]. This work proposes to explore and exploit structural modeling of the SPI module with an aim to reduce the number of Look-Up-Tables (LUTs) occupied, thereby reducing the area on chip in the analog front-end design. Amrut Anilrao Purohit, Mohammed Riyaz Ahmed, R. Venkata Siva Reddy Area Optimization using Structural Modeling for Gate Level Implementation of SPI for Microcontroller