Design and FPGA implementation of multiplierless comb lter Richa Barsainya, Meenakshi Agarwal* , and Tarun Kumar Rawat Division of ECE, Netaji Subhas Institute of Technology, New Delhi, India SUMMARY The main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb lter. Multipliers are the most area and power consuming elements; therefore, it is desirable to realize a lter with minimum number of multipliers. In this paper, design of comb lters based on lattice wave dig- ital lters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb lters (LWDCFs) are realized using Richardsand transformed rst-order and second-order all-pass sections. The resulting struc- tural realizations of LWDCFs exhibit properties such as low coefcient sensitivity, high dynamic range, high overow level, and low round-off noise. Multiplier coefcients of the proposed structures are imple- mented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A eld programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power con- sumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan-6 and Virtex-6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb lter structures. Copyright © 2017 John Wiley & Sons, Ltd. Received 22 July 2016; Accepted 30 December 2016 KEY WORDS: digital signal processing; comb lter; eld programmable gate array; Lattice wave digital lter; canonic signed digit code 1. INTRODUCTION A lter that has multiple pass-bands and stop-bands is known as comb lter. It notches out harmonic interferences while leaving the broadband signal unchanged. A comb lter has a frequency response that is a periodic function of ω with a period 2π L , where L is the positive integer. Comb lter nds application in the areas of communication, control and biomedical engineering to remove power line disturbances, and for the restoration of audio signals badly corrupted by periodic signals [15]. A comb lter is mainly designed by replacing z with z L in a transfer function H (z) of a lter having a single pass-band and/or stop-band. A comb lter can be generated from either a FIR or an innite impulse response (IIR) lter [3,6,7]. For linear phase applications, FIR lters are preferred but their efcient design requires higher number of coefcients compared with its IIR counterparts for the same specications. This results in increased computation complexity of FIR lters [8]. A comb lter designed using FIR systems has a design constraint that the notches have the relatively large bandwidth leading to attenuation of other frequency components around the desired nulls. Whereas, IIR comb lters provide much sharper notch band and require smaller number of arithmetic *Correspondence to: Meenakshi Agarwal, Room no: 135, ECE Division, Netaji Subhas Institute of Technology, Sector- 3, Dwarka, New Delhi 110075, India. E-mail: mishaagg@gmail.com Copyright © 2017 John Wiley & Sons, Ltd. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS Int. J. Circ. Theor. Appl. (2017) Published online in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.2324