JOURNAL OF ELECTRONIC TESTING: Theory and Applications 12, 29–39 (1998) c  1998 Kluwer Academic Publishers. Manufactured in The Netherlands. Efficient Totally Self-Checking Shifter Design RICARDO O. DUARTE ∗ , M. NICOLAIDIS, H. BEDERR AND Y. ZORIAN Reliable Integrated Systems Group, TIMA-46, Avenue, F´ elix Viallet, 38031, Grenoble, France; Texas Instruments, 06271, VilleneuveLoubet Cedex, France; and LogicVision, 101-Metro Drive, San Jose, CA 95110, USA Abstract. Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This work is aimed to reach these requirements for the design of self-checking shifters and is part of a broader project concerning the design of self-checking data paths. Keywords: self-checking circuits, on-line testing, parity prediction, fault-secure circuits 1. Introduction Self-checking designs [1] implement functional blocks delivering outputs belonging to an error detecting code. A checker monitoring this code performs error detec- tion concurrent to the normal circuit operation. Due to this concurrent error detecting ability self-checking (S-C) circuits are of high interest for applications re- quiring enhanced reliability. S-C circuits will gain in- creasing industrial interest if they can be implemented with reduced hardware cost and design effort and they can offer high fault coverage. This work concerns the design of low cost, high fault coverage self-checking shifters. In order to achieve reduced design effort the proposed solutions are implemented into a S-C shifters macro-block generator. This work is part of a broader effort concerning the development of low cost, high fault coverage solutions for S-C data paths, and the integration of these solutions into a CAD tool [2–4]. 2. Shifter Implementation Shifter units can be used for many different purposes: a simple division or multiplication by 2, an inversion of ∗ Under grant supported by CAPES-COFECUB. all bits or a simple signed arithmetic operation. Shifters can be implemented in different formats; such as barrel- shifters or multiplexer based. This work considers implementations using standard cells because they are becoming predominant in industrial context and also can be easily automated through the use of a HDL. Shifters can be implemented in their simplest form allowing to perform a one-position shift-left or shift- right. This case results on low hardware cost but re- quires k clock cycles to perform a k -positions shift. Alternatively shifters allowing to perform a shift of any number of positions per clock cycle increase per- formance significantly but of course hardware cost is also increased. According to the system requirements either of these solutions can be selected, so that the tool must include macro-blocks generators for both cases. Also the tool is able to provide shifters performing any combination of the following operations: rotation, left or right logic shift and arithmetic shift. Since we have decided to work in a standard cell environment our basic option concerns shifters based on multiplexers. Barrel shifters are also considered at the end of the paper, since they could be chosen in some applications requiring a better speed perfor- mance. Area/performance efficient shifter designs [5] are considered below. An illustration of this imple- mentation is shown in Fig. 1.