A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits Amit Jain • Arpita Ghosh • N. Basanta Singh • Subir Kumar Sarkar Received: 15 May 2014 / Revised: 8 January 2015 / Accepted: 10 January 2015 / Published online: 21 January 2015 Ó Springer Science+Business Media New York 2015 Abstract To explore single-electron circuits for different applications, a proper simulation platform where circuits consisting of single electron transistors and other devices can be simulated efficiently is needed. A macro model of single electron transistor featuring symmetric tunnel junc- tions is proposed. In the proposed model, a voltage con- trolled current source is incorporated in the existing model of SET to get more accurate results. Three scaling factors have been included in the model to improve the versatility of the model. The advantages and disadvantages of dif- ferent simulation methods are discussed as a justification for choosing the macro model approach. The proposed model can efficiently describe the physical phenomena occurring in coulomb blockade and coulomb oscillation regions. The SPICE environment is used for the simulation and to verify the accuracy, the model is applied to a single electron inverter circuit and the effect of macro model parameters on the noise margin is investigated to estimate the robustness of the inverter cell. A multi peak negative differential resistance circuit based on the proposed macro model is designed and demonstrated. Also, an integrator circuit has been designed to prove the validity of the pro- posed model in the analog domain. Further, the linearity of the integrator circuit is analyzed through harmonic and intermodulation distortion analysis. Keywords Single electron transistor (SET)  Macro model  SPICE  SIMON  Inverter  Noise margin  Multi peak negative differential resistance (NDR) circuit  Integrator circuit  Harmonic and intermodulation distortion 1 Introduction Single electronics is nothing but the controlled manipulation of individual electrons through a barrier. Though the journey of single electronics started long ego by Robert Millikan who manipulated single electron onto oil drops in the early 1920s, it took almost 70 years to put its footprint in the solid state technology. Single electron transistor (SET) is the most promising candidate for future VLSI/ULSI solutions [1–4]. Several works have been reported in the literature on SET based circuit designs [5–10]. Some works have also been reported on hybrid SET–MOS circuit design [11–18]. To design and analyze single-electron circuits efficiently, we need a proper simulation environment, which will allow us to study the characteristics and have potential to compete with other existing technologies. As Monte Carlo based simulators take significant time to simulate circuits and don’t support the hybrid SET–MOS simulations, researcher have been looking for other modeling approaches [19–24] to efficiently simulate single-electron based circuits. Basically there are three dif- ferent approaches to the simulation of single electronics circuits: SPICE macro-modeling, Monte Carlo based method and master equation method. The Monte-Carlo method is a probabilistic approach where the result is achieved by sto- chastic integration [25]. In this method, random tunnel times are computed for all possible events and correlation in these Pseudo random numbers can affect the result drastically [26]. As this method includes stochastic sampling, it takes a long A. Jain (&)  S. K. Sarkar Jadavpur University, Kolkata 700032, West Bengal, India e-mail: amit2_8@yahoo.co.in A. Ghosh RCCIIT, Kolkata 700015, West Bengal, India N. B. Singh Manipur Institute of Technology, Manipur University, Imphal 795004, Manipur, India 123 Analog Integr Circ Sig Process (2015) 82:653–662 DOI 10.1007/s10470-015-0491-5