Chennai and Dr.MGR University Second International Conference on Sustainable Energy and Intelligent System (SEISCON 2011) , Dr. M.G.R. University, Maduravoyal, Chennai, Tamil Nadu, India. July. 20-22, 2011. 605 Design and Implementation of a Hybrid SET-CMOS based Hi-speed and power efficient Pulse Divider Circuit Anindya Jana 1 , N Basanta Singh 2 , Anup Sarkar 4 , J.K. Sing 3 and Subir Kumar Sarkar 1 1 Department of Electronics & Telecommunication Engineering, Jadavpur University, Kolkata-700032, India 2 Department of Electronics & Communication Engineering, Manipur Institute of Technology, Imphal -795004, India 3 Department of Computer Science and Engineering, Jadavpur University, Kolkata-700032, India 4 Women’s Polytechnic, Kolkata-68, India. (anindya.jana@rediffmail.com, basanta_n@rediffmail.com, su_sircir@yahoo.co.in) Keywords: Single Electron Transistor, CMOS, Hybrid CMOS- SET Circuits, MIB, T-Spice. Abstract Hybrid SET-CMOS circuits which combine the merits of both the SET and CMOS promises to be a practical implementation for fu- ture low power ultra-dense VLSI/ULSI circuit design. In this work, an SET-CMOS hybrid pulse divider circuit is proposed. The MIB model for SET and BSIM4 model for CMOS are used. The opera- tion of the proposed circuit is verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based pulse divid- er circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit. 1 Introduction Scaling down of CMOS transistor size has pushed CMOS tech- nology toward the deep sub-50nm regime [1]. However, there have been reports suggesting that the MOS transistor can not shrunk beyond certain limits dictated by its operating principle [2]. Over recent years this realization has led to exploration of possible successor technologies with greater scaling potential such as resonant tunnelling devices [3], carbon nanotube devices [4], [5], nanowires [6], and single-electron tunneling devices [7], [8]. Single-electron transistors (SETs) are promising for VLSI/ ULSI circuits due to their ultra-low power consumption and ultra- small feature size scalability [9]. The real problems preventing the use of SETs in most applications are their low current drivability, small voltage gain, high output impedance, and high sensitivity to background charges. Since CMOS devices have advantages that can compensate for the drawbacks of SETs, hybrid SET-CMOS circuits that combine both SET and CMOS devices is one of the possible solutions to the problems of SET mentioned above. With hybrid CMOS-SET, a lot of new functionalities can also be achieved with few devices [10]. Pulse divider is an electronic device that reduces by an integral factor the frequency of periodic oscillations applied to it. Fre- quency dividers are used in frequency synthesizers, in quartz- crystal and atomic clocks, in television apparatus (to synchronize scanning generators), and as timing devices in radar. Electronic counters, self-excited sine-wave generators, regenerative devices, self-excited oscillators with phase-locked frequency control, and relaxation generators are used to divide frequencies. In a self- excited sine-wave generator, frequency division is achieved by synchronizing the generator’s frequency with a sub harmonic os- cillation of the frequency of the external periodic signal by means of the locking effect. To divide the repetition rate of the pulse sig- nals, relaxation generators are used as frequency dividers. These generators (multivibrators and blocking oscillators) operate in the periodic mode, with the pulse-repetition rate locked onto a sub- harmonic frequency, or in the driven mode, with a pulse-repeti- tion period k times higher. In practice k does not exceed 10. In this work, hybrid CMOS-SET pulse divider circuit is proposed. The operation of the proposed circuit is verified in Tanner environ- ment. The MIB compact model for SET devices and BSIM4.6.1 model for CMOS are used. 2 Single Electron Transistor Single Electron Transistors (SETs) are made by placing two tun- nel junctions in series. The two tunnel junctions create what is known as a “Coulomb island or Quantum dot” that electrons can only enter by tunnelling through one of the insulators. A sche- matic structure and equivalent circuit of an SET is shown in Fig. 1. This device has three terminals like an ordinary Field Effect Transistor: source, drain and gate. The gate terminal is capaci- tively coupled to the node between the two tunnel junctions. The electrical behavior of tunnel junction depends on how effectively barrier transmit the electron wave, which depends on thickness and on the number of electron waves modes impinge on the bar- rier, which is given by the area of tunnel junction divided by the square of wave length. In a Quantum dot [QD] addition or removal of a single electron can cause a change in the electrostatic energy or Coulomb energy. This energy is greater than the thermal energy and can control the electron transport into and out of the QD. This sensitivity to individual electron has led to electronics based on single elec- trons. Even only one electron tunnelling may produce a charge e/C across the tunnel junction (where C is total capacitance and e = 1.602 x 10-19 C). The critical voltage Vc, which is the threshold