A proposed DG-FinFET based SRAM cell design with RadHard capabilities S.S. Rathod * , A.K. Saxena, S. Dasgupta Department of Electronics and Computer Engineering, Indian Institute of Technology Roorkee, Uttarakhand 247 667, India article info Article history: Received 24 November 2009 Received in revised form 20 April 2010 Available online 13 May 2010 abstract The radiation induced soft errors have become one of the most important and challenging failure mech- anisms in modern electronic devices. This paper proposes a new circuit level hardening technique for reduction of soft error failure rate in DG-FinFET (double gate FinFET) based static random access memory (SRAM). Analysis for 32 nm and 45 nm technology nodes is carried out. It is inferred from the paper that the proposed SRAM cell outperforms over DICE latch in terms of fault tolerance of external data and con- trol lines, power dissipation and fast recovery when exposed to radiation for both the technology nodes. This is primarily due to the addition of extra transistors used to neutralize the effect of single event upset without affecting normal operations. Transistor count increase the area and write delay by 7% and 20% respectively over that of DICE latch. While read delay decreases by 14% for the proposed SRAM cell. Ó 2010 Elsevier Ltd. All rights reserved. 1. Introduction SRAM when used in space applications or nuclear applications is required to have both high operating performance and good hardness to radiations. Protection against single-event-effects is very important for space applications, biomedical applications, enterprise computing and communication applications since the system-level soft error rate (SER) has been rising with technology scaling and increasing system complexity. Several techniques ranging from the process-level [1,3,4], device-level [2], circuit level [6,7], and system level [8–10] are reported to improve single event upset (SEU) reliability. At the circuit level, increasing the critical charge of a circuit node and adding the transistors to enable the redundant storage of information are the two main approaches to reduce the effects of soft errors. These techniques tend to in- crease the power consumption and lower the speed of the circuits. Redundant circuit techniques include the low power cell [5], Triple module redundancy (TMR) [6] and DICE [7]. These redundant tran- sistor based designs usually require at least twice as many transis- tors as unprotected circuits, which typically indicate very high area and power penalties. Though the area and power penalties are not minimized, the proposed design is more hardened as compared to the above techniques. The challenges pose by 45 nm and finer technologies in the bulk CMOS along with the limited solutions raise the urgency to inves- tigate the new structures and devices. Numerous solutions have been proposed in literature to deal with these issues such as an additional parasitic capacitance at the storage nodes [8–10], dou- ble-Vt transistors, high-Vt transistors being used in the memory cell and low-Vt transistors in the peripherals [11] and finally dual V dd with higher V dd dedicated to the cell. All of these techniques can be combined, i.e. a high V dd and high Vt for the cell, which im- proves the stability, the SER, the performance and finally the power consumption. However these techniques are conflicting with the technology scaling that aims to take maximum advantage of fea- ture size reduction. Several techniques used to protect SRAMs are based on bulk CMOS or single gate SOI technologies. According to the ITRS 2007 edition [12], planar bulk CMOS will require high channel doping in order to maintain acceptable electrostatic control of the channel and will face increased band-to-band tunneling, gate induced drain leakage (GIDL) and large variability, induced by statistical fluctua- tions of channel doping level. An alternative solution consists in employing field-effect transistors on Silicon on Insulator (SOI). Multiple gate transistor architectures are expected for the 45 nm or the 32 nm technology node, mainly because they provide a much better electrostatic control than conventional bulk silicon devices. Popularity of multiple gate circuits motivated us to design SRAM using nonconventional devices like DG-FinFET as shown in Fig. 1. However, memory protection against single event is not realized enough for designs manufactured in advanced nonconven- tional technologies like double gate and DG-FinFET circuits. It is a well known fact that 6T SRAM cell based on DG-FinFET structure fails under irradiation. This motivates us to propose circuit level hardening technique for the SRAM cell based on DG-FinFET structure. In SRAM cell, the collection of charge generated in a radiation event can be modeled as a current pulse connected between the high logic level storage node and the ground. We have injected a 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.04.020 * Corresponding author. E-mail address: sudebfec@iitr.ernet.in (S.S. Rathod). Microelectronics Reliability 50 (2010) 1181–1188 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel