International Journal of Engineering & Technology IJET-IJENS Vol:09 No:10 19 92510-7474 IJET-IJENS © December 2009 IJENS I J E N S Simulation Analysis of an Effective Gate Drive Scheme for a New Soft-Switched Synchronous Buck Converter N. Z. Yahaya, K. M. Begam, and M. Awan Abstract -- This paper proposes a new resonant gate driver circuit for a soft switching synchronous buck converter in a fixed load condition. The switching energy can be fully recovered during current commutation phase in the gate driver while the diode conduction losses in the low and high side switches can be substantially reduced by employing additional L and C resonant in the circuit. Using PSpice simulation, the optimization technique has been studied. From the predetermined pulse width of the generated signals, the optimized resonant inductor current is observed to generate less oscillation and hence lower the switching loss. In addition, an optimized dead time interval is inserted between high side and low side of the transistors in the synchronous buck converter to minimize their body diode con duction losses. The detailed operations of both circuits are analyzed. Index Term— PSpice Simulation, Resonant Gate Driver, Soft Switching, Synchronous Buck Converter, ZVS I. INT RODUCT ION There has been an increasing research in pulse-width modulation (PWM) converter’s design especially at high switching frequency. At this level of frequency, it gives the pleasure in fast transient response, reduces the size of components and generates superior power density. However, the switching loss and gate loss will increase tremendously [1]. Most importantly, specific PWM designs are only meant for specific applications. In synchronous buck converter (SBC) circu it, for e xa mple, the implementation of gate driver using PWM technique is required. Even though the predictive scheme is available in a chip-based module nowadays, the traditional fixed pulse scheme is still preferred due to its simplicity and easy in the design phase. This also includes the additional soft- switching operation in reducing switching losses. Clearly, there are two parts; one is the gate driver design and the other, the soft-switching technique which will be applied to the SBC circuit. This will increase efficiency and overall performance of the converter. In this work, a high power MOSFET is used in resonant gate drive (RGD) circuit. In operating at high frequency, RGD presents many limitations, tradeoffs and drawbacks. The duty ratio, D, dead time, T D and the resonant inductor, L r are significant in achieving high frequency gate drive operation. The diode-clamped (DC)-RGD circuit is used in N. Z. Yahaya is with Universiti Teknologi PETRONAS, Malaysia. Currently he is pursuing PhD in the field of Power Electronics. He can be contacted by Tel: 605-368-7823; fax: 605-365-7443 (e-mail: norzaihar_yahaya@petronas.com.my) K. M.Begam is a lecturer specializing in Physics and currently attached with Universiti Teknologi PETRONAS, Malaysia (e-mail: mumtajbegam@petronas.com.my). M. Awan is with the Electrical Engineering Department, Universiti Teknologi PETRONAS, Malaysia. His research interest is in the area of Analog IC Circuit Design.(e-mail: mohdawan@petronas.com.my). the analyses which is shown in Fig. 1, tested in an inductive load system. It has a full capability in recovering energy in the circuit without producing high dissipation at the input. DC VP 1 VP 2 V s L r D x D y Load Q x Q y Fig. 1. DC-RGD circuit In most of RGD circuit designs [2-9], switching losses of the driving switches contribute to the most losses compared to conduction and gate losses. In the circuit, VP 1 and VP 2 are the two separate pulse generators which provide complementary square wave signals to either switch Q x and Q y . The switching frequency applied is 1 MHz. In high switching frequency, the switches experience high stress and hence dissipate more heat. Basic work has been reported in [10]. Using proper pulse generation from VP 1 and VP 2 respectively, the conduction of Q x and Q y will produce the waveforms as shown in Fig. 2. The basic operation of the DC-RGD circuit is as follows. When switch Q x turns on, the inductor current, i Lr develops. At this time, Q y is off. Here, i Lr is charged exponentially to maximum value and so is gate voltage of S, V gs,S of which it is clamped to input source, V s of 12 V. Time 192.95us 193.00us 193.05us 193.10us 193.15us 193.20us 193.25us 193.30us 193.35us 193.40us 193.45us V(S1:g,S1:s) I(Lr) 0 5.0 10.0 13.9 SEL>> Duty Ratio Resonant inductor current, iLr Vgs of S1 power MOSFET V(Q2:g,Q2:s) V(Q1:g,Q1:s) 0V 2.5V 5.0V Dead time Switch Q1 - OFF Switch Q2 - ON Switch Q2 - OFF Switch Q1 - ON Fig. 2. Operating Waveforms of DC-RGD circuit iLr Vgs, S Cin