Microelectronics and Solid State Electronics 2013, 2(2): 29-38 DOI: 10.5923/j.msse.20130202.03 Optimization of High Performance Bulk FinFET Structure Independent of Random Dopent Process Variations S. L. Tripathi * , Ramanuj Mishra, R. A. Mishra Department of Electronics and Communication Engineering , MNNIT, Allahabad Abstract FinFETs are multigate MOSFETs conventionally fabricated on SOI wafer. Alternatively, use of Si-bulk wafers for FinFET has gained significant interest for the low cost of wafers and more importantly for the compatibility with bulk CMOS technology. This paper describes the design of Bulk FinFET with improved performance using different bulk structures. In initial part of work, we have used the Pie- gate structure and heavy body doping structure i.e. Punchthrough stopper. Both the structures are combined in a novel Pie-gate bulk FinFET structure with punchthrough stopper. It has been observed that the novel structure shows better results compared to previous structures but it is difficult to fabricate. So, the Performance of bulk FinFET with bottom spacer is studied including the detailed discussion of process variation effect which shows that such bulk structure is supposed to have less fabrication complexity to achieve and optimize a desired doping profile. Finally, It is observed that the bulk FinFET with bottom spacer can be optimized to obtain superior performance than all other FinFETs making it independent of doping related process variations. Keywords Bulk (FinFET), Subthreshold Performance, Punchthrough Stopper, Bottom Spacer(BS), Active Fin Length, Width Quantization, SOI FinFET, Sentaurus TCAD Device Simulator 1. Introduction Conventionally FinFET[1] is fabricated on SOI wafer[2-3] because of its excellent short channel characteristics but SOI wafer shows some disadvantageous over bulk FinFET like floating body effect , heat transfer problem and high wafer cost[4]. Bulk FinFET[5] covers most of the drawbacks of SOI FinFET. Also, bulk FinFET shows better immunity to negative bias-temperature (NBT) stress[6]. Additionally, Bulk FinFET has gained attention due to its low-cost process and the ability to be integrated with standard bulk CMOS technology[7-8]. But the characteristics of bulk FinFET are not comparable with SOI FinFET. One major advantage of SOI over bulk is speed. SOI devices have 30% speed advantage over their bulk counterpart in normal MOSFET. But it has been reported[9] that owing to their geometry (i.e.3D structure) for significantly (~60nm) large Fin height, less than 5% delay difference is obtained. For Fin height of 30nm this delay difference becomes approximately 8%. Therefore, we can say that speed advantage in SOI FinFET is not prominent as it is in normal SOI MOSFET leading to the importance of bulk FinFET structures of comparable * Corresponding author: tri.suman78@gmail.com (S. L. Tripathi) Published online at http://journal.sapub.org/msse Copyright © 2013 Scientific & Academic Publishing. All Rights Reserved performance parameters.. The Bulk FinFETs are fabricated with high body doping to suppress source to drain coupling effect[10] However, the lack of isolation layer underneath the transistor body allows the drain field to penetrate towards the source more easily by deteriorating the subthreshold slope and DIBL. Use of high channel doping is used to reduce OFF state current to improve performance of bulk FinFET. But this will result in significant mobility degradation and high parasitic capacitances[9]. Although bulk FinFET shows excellent promise but it does not have performance as good as SOI FinFET. So, it is important to optimize bulk FinFET performance as in SOI FinFET. Previously, Pie-gate bulk FinFET i.e. isolation oxide with source/drain-to-body (S/D) junctions shallower than gate-bottom[11] and bulk FinFET of heavy body doping i.e. Punchthrough stopper, is reported[9]. Here Pie-gate structure is basically represented by misalignment(ΔX j =-ive) between the S/D junctions and the bottom of the gate electrode. Since the change of performance due to process variation can be very undesirable for some analog or digital CMOS circuits, the designer wants that the device performance should be independent of process variation[12]. The observed random distribution of identically drawn devices can be caused by impurity concentration densities. This results from non-uniform conditions during the deposition and the diffusion of the impurities(dopant) and the changes in these parameters cause electrical parameters to vary, such as sheet