664 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 9, NO. 6, NOVEMBER 2010 Research Letters Threshold Voltage Variations Make Full Adders Reliabilities Similar Walid Ibrahim, Senior Member, IEEE, and Valeriu Beiu, Senior Member, IEEE Abstract—Addition is the most widely used arithmetic opera- tion in digital applications. The reliability of full adder (FA) cells is crucial as they affect arithmetic logic and floating-point units, as well as cache/memory address calculations. This letter studies the reliability of five different FA designs. The analysis starts from the device level by estimating the effects threshold voltage variations will have on the reliability of scaled CMOS transistors. These es- timations will then be used to calculate the reliability of the sum and carry_out signals. This letter will also briefly explore the ef- fects of increasing the reliability of devices and of using gate-level redundancy schemes on the reliability of FAs. Index Terms—Adders, Bayesian network (BN), CMOS, reliabil- ity, threshold voltage, variations. I. INTRODUCTION A DDITION is by far the most widely used arithmetic op- eration in today’s digital applications. Besides the basic addition operation, full adder (FA) cells are essential building blocks for many other operations including subtraction, mul- tiplication, division, and address calculations. Therefore, their performances are crucial, affecting the overall performances of the systems they are a part of. At the same time, the sus- tained massive growth of the mobile appliances market is push- ing the demand for power-efficient VLSI circuits. This was the main driving force behind many research papers during the last decade [1]–[3]. The main design objective of such papers has constantly been to create faster FA cells while also reducing their power consumption. All of these designs implicitly assumed that the gates themselves are reliable (enough); therefore, reliability was never considered as one of the optimization criteria. The latest ITRS predicts that reliability issues are going to be one of the greatest threats to scaling [4], which should be- come difficult when going beyond 10 nm as many more “errors [will] arise from the difficulty of providing highly precise di- Manuscript received March 6, 2010; revised May 26, 2010; accepted July 12, 2010. Date of publication August 16, 2010; date of current version November 10, 2010. The review of this paper was arranged by Associate Editor D. Hammerstrom. W. Ibrahim is with the Faculty of IT, United Arab Emirates University, Al Ain 17551, Abu Dhabi, UAE, and also with the Department of Systems and Computer Engineering, Carleton University, Ottawa, ON K1S 5B6, Canada (e-mail: walidibr@uaeu.ac.ae). V. Beiu is with the Faculty of IT, United Arab Emirates University, Al Ain 17551, Abu Dhabi, UAE, and also with the School of Computing and In- telligent Systems, University of Ulster, Coleraine BT52 1SA, U.K. (e-mail: vbeiu@uaeu.ac.ae). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNANO.2010.2066573 mensional control needed to fabricate the devices and also from interference from the local environment.” From the process perspective, CMOS scaling has been used successfully over the last four decades to improve the perfor- mance of VLSI designs. With CMOS geometries shrinking below 32 nm, the available reliability margins are drastically being reduced as the CMOS transistors are introducing larger- and-larger parameter fluctuations/variations [5]. These lead to device-to-device fluctuations in key parameters, including the threshold voltage (V th ) [6]. In this letter, the effect of V th variations on the reliability of five FAs is thoroughly investigated, and two approaches to improve on their reliability (by improving the reliability at both the device and the gate levels) are analyzed. The rest of the letter is organized as follows. The state of the art is presented in Section II. Accurate FA reliability calculations are discussed in Section III, followed by simulation results in Section IV. Concluding remarks are provided in Section V. II. STATE OF THE ART Very recently, the reliability of (future) nanoscale FA cells has attracted the attention of several research teams [7]–[13]. The probability transfer matrix technique has been used in [8] and [9] to evaluate the reliability of FAs implemented with quantum-dot cellular automata (QCA). The simulation results showed that the FA should have a probability of failure (PF) less than 10 −7 in order to reach 99% reliability for a 128-bit ripple carry adder [8]. This is inline with simulations results from [9], which showed that PF GATE should be below 10 −7 in order to achieve 99.999% reliability for a 2-bit adder. Monte Carlo (MC) simulations have been used in [10] to evaluate the energy and reliability of four different FAs. The authors concluded that reliability and energy become closely linked in ultra-low power regimes and error-aware logic design can produce a great reduction in energy consumption. In [11], Choi et al. used binary decision diagram (BDD) to design a new single-electron transistor FA cell. They used MC simulations to study the sensitivity of the proposed FA to process variations. The sensitivity of the proposed FA was also compared to the sensitivity of a majority (MAJ) based and a threshold logic gate (TLG)-based FA. The simulation results showed that the BBD FA can tolerate 2.85 times and 4 times more background charge variations than the MAJ and the TLG FAs, respectively. MC simulations were also used by Stanisavljevic et al. [12] to investigate the effect of introducing hardware re- dundancy on the reliability of a standard CMOS (mirrored) 4-bit 1536-125X/$26.00 © 2010 IEEE