Data Path Integration 136 0740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers THE LIMITATIONS OF conventional processor archi- tectures are becoming increasingly evident. The growing importance of stream-based applications makes coarse- grained, dynamically reconfigurable architectures an attractive alternative. 1-8 They combine the performance of ASICs, which are risky (in terms of flexibility and usabil- ity, because of fixed functional sets) and expensive (in development and mask costs), with the flexibility of tra- ditional processors. In spite of today’s VLSI possibilities, basic micro- processor architecture concepts are still the same as 20 years ago. Conventional microprocessors’ main pro- cessing unit, the data path, follows the same style guide- lines as its predecessors. Although the development of pipelined architectures or superscalar concepts in com- bination with data and instruction caches increases a modern microprocessor’s performance and allows high- er frequency rates, the main concept of a static data path remains. Therefore, each instruction is a compo- sition of the processor’s basic operations. The processor concept is beneficial because it sup- ports the execution of strongly control-dominant appli- cations. Data- or stream-oriented applications are not well suited to this environment. These applications are not the right target for sequential instruction execution, which requires very high bandwidth for permanently retransmitting instructions or data words from and to memory. Using caches in different stages usually over- comes this handicap. A sequential inter- connection of filters that manipulate the data without writing back the intermedi- ate results would achieve the right opti- mization and dramatically reduce the required bandwidth. In practice, this fil- ter chain should be constructed logical- ly and configured at runtime. Existing approaches extending instruction sets use static modules that are not modifi- able at runtime. 9 Customized microprocessors or ASICs are optimized for one special application environment. It is inefficient to use the same optimized core for different application domains and thus lose the desired performance gain of the customized architecture. Instead, we need a new approach based on a flexible, high-performance data path. This approach would offer reconfiguration func- tionality and make the core largely application inde- pendent without losing the performance needed for stream-based applications. To develop such an approach, we loosely coupled Pact XPP Technologies’ dynamic, reconfigurable Extreme Processing Platform (XPP) architecture into the static data path of the general-purpose Leon processor. There are some approaches in which the XPP operates as a completely separate (master-slave) component within a configurable SoC, along with a processor core, global/local memory topologies, and efficient multilayer AMBA advanced high-perfor- mance bus (AHB) interfaces. By contrast, in our approach, the extended and adapted data path looks to the programmer like a dynamically configurable instruction set. The programmer can customize the instruction set for a specific application, thus greatly accelerating execution. The programmer can create several configurations and upload them to the XPP array at runtime to use as a filter for calculating Scalable Processor Instruction Set Extension Editor’s note: Coarse-grained reconfigurable platforms are good for parallel data-intensive applications but inefficient for sequential control-dominated code. This article (selected from the best of the SBCCI 2003 papers) explores the integration of the general-purpose, Sparc-compliant Leon processor with the Extreme Processing Platform reconfigurable data path. The integration’s goal is to optimize the execution of complex multimedia applications such as MPEG-4. —Fadi J. Kurdahi, University of California, Irvine Jürgen Becker and Alexander Thomas University of Karlsruhe