Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring Gianpiero Cabodi, Paolo Camurati, Stefano Quer * Politecnico di Torino, Dipartimento di Automatica e Informatica, corso Duca degli Abruzzi 24, 10129 Turin, Italy Accepted 14 October 2000 Abstract Reachability analysis is an orthogonal, state-of-the-art technique for the veri®cation and validation of ®nite state machines FSMs). Due to the state space explosion problem, it is currently limited to medium-small circuits, and ex- tending its applicability is still a key issue. Among the factors that limit reachability analysis, let us list: the peak binary decision diagrams BDD) size during image computation, the BDD size to represent state sets, and very high sequential depth. Following the promising trend of partitioning, we decompose a ®nite state machine into ``functioning-modes''. We operate on a disjunctive partitioned transition relation. Decomposition is obtained heuristically based on com- plexity, i.e., BDD size, or functionality, i.e., dividing memory elements into ``active'' and ``idle'' ones. We use an im- proved iterative squaring algorithm to traverse high-depth subcomponents. The resulting methodology attacks the above problems, lowering intermediate peak BDD size, and dealing with high-depth subcomponents. Experiments on a few industrial circuits and on some large benchmarks show the feasibility of the approach. Ó 2001 Elsevier Science B.V. All rights reserved. Keywords: Symbolic techniques; BDDs; Circuit partitioning and decomposition; Reachability analysis 1. Introduction Exploring the state space of a ®nite state ma- chine FSM) allows us to prove many useful properties. Among them, let us list equivalence [1], resetability [2], and synchronization [3]. Given two FSMs, proving or disproving the equivalence of their input/output behavior has applications to several ®elds, namely automated synthesis [4±6], formal veri®cation of correctness [7,8], test pattern generation [9], and redundancy identi®cation [9,10]. State-of-the-art approaches for state space ex- ploration of FSMs exploit symbolic techniques based on binary decision diagrams BDDs) [11,12]. These techniques, albeit much more ecient than explicit methods, reach their limits on large prac- tical examples. Recent eorts have focused on making them applicable to larger and more real- istic circuits. Among these eorts, we list the fol- lowing. · Transition relations have been represented and used in partitioned form [7,13], because of BDD explosion when building them in mono- lithic form. · Dynamic reordering techniques [14] have been proposed to dynamically ®nd good variable orders, with large improvements whenever www.elsevier.com/locate/sysarc Journal of Systems Architecture 47 2001) 163±179 * Corresponding author. E-mail address: quer@polito.it S. Quer). 1383-7621/01/$ - see front matter Ó 2001 Elsevier Science B.V. All rights reserved. PII:S1383-762100)00064-3