Copyright © 2018 Authors. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. International Journal of Engineering & Technology, 7 (2.8) (2018) 195-200 International Journal of Engineering & Technology Website: www.sciencepubco.com/index.php/IJET Research Paper Efficient high throughput decoding architecture for non-binary LDPC codes C. Arul Murugan 1*, B. Banuselvasaraswathy 2 , K. Gayathree 3 , M. Ishwarya Niranjana 4 1 Assistant Professor, Department of ETE, Karpagam College of Engineering, Coimbatore, India 2, 3 Assistant Professor, Department of ECE, Sri Krishna College of Technology, Coimbatore, India 4 Assistant Professor, Department of ECE, Pollachi Institute of Engineering and Technology, Pollachi, India. *Corresponding author E-mail: murugan.carul@gmail.com Abstract This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz. 1. Introduction In today’s modern era [3], communication has entered into day to day lives in various forms. Communication is the method of exchanging information in form of message, information between sender and receiver. Therefore, various technologies are developed for increasing long range communication and automatic data processing equipment. High throughput and effective data transmission with minimum error rate is needed for the design. Following, a lot of error controlling techniques have been introduced for error detection and correction. LDPC (Linear Density Parity Check) is one kind of techniques used. LDPC codes are good enough with high potential to support decoder that exhibit parallel operation. In mobile communications, the channel decoder should have the ability to assist different code rates and automatic error correction capability. To design efficient multimode decoder, closeness among different modes are identified, analyzed and designed as reusable hardware devices to increase the flexibility of entire architecture. These features are incorporated into a fully parallel architecture adopted in multimode LDPC decoder designs. LDPC codes are employed in order to control the errors. Furthermore, it is appropriate for implementations in decoder that that show a substantial utilization of parallelism. Moreover, Trellis modulation scheme is a used for efficient transmission of data over a band limited channels which is widely used for application with high throughput and better error controlling techniques. Hence, a trellis dependent decoding architecture for non-binary LDPC (Linear Density Parity Check) code was designed. 2. Related Works In this article, non-binary LDPC codes are preferred than binary low density parity check (LDPC) codes because of high coding gain. Binary LDPC codes fail to achieve near-capacity performance in small or medium code length. Hence, decoding architecture is designed for non – binary LDPC codes. Injae et al[1], brings out a low-power low-density parity check convolutional code (LDPC-CC) decoder. This design combines several memory banks into single memory bank in order to diminish the power consumption. Wang et al[2] discussed about the incorporation of new parallel interleave techniques for turbo decoder. It utilizes quadratic permutation polynomial (QPP) interleaver for the cross MAP (XMAP) parallel decoding and symbol-based serial MAP (SMAP). In [6], Davey et al introduced aq-ary Sum-Product algorithm (QSPA). The algorithm is appropriate for non binary LDPC codes. This algorithm is suitable for implementation in probability domain. QSPA is an extension of SPA (sum Product Algorithm) for binary codes. QSPA algorithm is difficult to implement in log domain because it is easily affected by quantization effects and needs complex multiplication operation. Wymeersch et al[7] , proposed implemented QSPA in the log domain and named as Log-QSPA. In this algorithm, multiplication process is replaced by addition which in turn eliminates the normalization factor. In log QSPA, each and every check node processing is carried out by Brute force technique. From the results, it is inferred that when the check node is high, the check node processing in log QSPA is still considered to be a tedious task. In [8] author utilized Fast Fourier Transform (FFT) in QSPA implementation, therefore it is named as FFT-QSPA, even though this algorithm reduces the complexity but still it requires improvement for multiplication operation in the probability domain. algorithm reduces the complexity but still it