Fabrication of the buried channel polycrystalline silicon TFT Cheol-Min Park, Min-Koo Han* Room 1102, School of Electrical Engineering, Seoul National University, Seoul, South Korea Received 14 January 1999; received in revised form 28 February 1999; accepted 5 March 1999 Abstract A new poly-Si TFT called `the buried channel poly-Si TFT (BCTFT)' with four-terminals has been proposed and fabricated. The BCTFT exhibits performance superior to the conventional poly-Si TFT in on-current and ®eld eect mobility due to moderate doping at the buried channel. The o-state leakage current is reduced to the level of conventional poly-Si TFT leakage currents due to the suppression of drift carriers by junction depletion between the moderately doped buried channel and the counter-doped body region. We have fabricated a 23-stage CMOS inverter chain (ring oscillator) in order to examine the dynamic characteristics of the BCTFT. The oscillation frequency of the CMOS inverter chain with a BCTFT is much higher than that of conventional poly-Si TFTs due to high on-current and device mobility. # 1999 Elsevier Science Ltd. All rights reserved. Keywords: Polycrystalline silicon; Thin ®lm transistor; Buried channel; Mobility; Leakage current; Junction depletion; CMOS; Inverter chain; Ring oscillator 1. Introduction Low temperature processed polycrystalline silicon thin ®lm transistors (poly-Si TFTs) have attracted much attention in various large areas of electronics such as ¯at panel displays [1], page width optical scan- ners and page width printer heads [2]. In conventional poly-Si TFTs, the drain has to be osetted from the channel region in order to achieve a low leakage cur- rent [3]. However, this causes a severe current pinching problem, resulting in high on-resistance. Recently, a ®eld plated high voltage TFT was proposed to solve this problem [4]. It oers higher current driving capa- bility without the increase of the leakage current. However, this approach results in a complicated device structure and biasing scheme. In addition, the current driving capability and the switching speed are most im- portant in poly-Si TFT-LCD panel applications. It is well known that the buried channel MOSFETs have higher mobility than surface channel devices [5]. The purpose of this work is to adapt the buried channel structure for a poly-Si TFT in order to increase the on-current and obtain a higher switching speed. 2. Device structure and fabrication We propose a fabrication method for CMOS poly-Si TFTs with a buried channel (BCTFT). The buried channel is formed by the ion implantation of counter dopant on the bottom active layer prior to top active Solid-State Electronics 43 (1999) 1785±1789 0038-1101/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S0038-1101(99)00122-7 * Corresponding author. Tel.: +82-2-880-7248; fax: +82-2- 883-0827. E-mail address: mkh@eesrc-09.snu.ac.kr (M.K. Han)