Quantitative Two-Dimensional Carrier Mapping in Silicon Nanowire-Based Tunnel-Field Effect Transistors Using Scanning Spreading Resistance Microscopy Andreas Schulze 1,2 , Thomas Hantschel 1 , Pierre Eyben 1 , Anne Vandooren 1 , Rita Rooyackers 1 , Jay Mody 1,2 , Anne S. Verhulst 1,3 and Wilfried Vandervorst 1,2 1 IMEC, Kapeldreef 75, 3001 Leuven, Belgium, 2 KU Leuven, Dept. of Physics and Astronomy, Celestijnenlaan 200D, 3001 Leuven, Belgium 3 KU Leuven, Dept. of Electrical Engineering, Kasteelpark Arenberg 10, 3001 Leuven, Belgium ABSTRACT The successful implementation of silicon nanowire (NW)-based tunnel-field effect transistors (TFET) critically depends on gaining a clear insight into the quantitative carrier distribution inside such devices. Therefore, we have developed a method based on scanning spreading resistance microscopy (SSRM) which allows quantitative two-dimensional (2D) carrier profiling of fully integrated NW-based TFETs. The keys in our process are optimized NW cleaving and polishing steps, in-house fabricated diamond tips with ultra-high resolution, measurements in high-vacuum and a dedicated calibration procedure accounting for dopant dependant carrier mobilities and surface states. INTRODUCTION Nanowire (NW) based tunnel-field effect transistors (TFETs) are considered as one of the most promising successors of standard metal-oxide-semiconductor field effect transistors (MOSFET) due to reduced short-channel effects and the absence of a 60 mV/decade subthreshold swing limitation. 1 To support the development of adequate doping processes while being faced with decreasing dimensions of the NWs, there is a need for characterization techniques with high spatial resolution (in the nanometer range), high dopant gradient resolution (2-3 nm/decade) and high sensitivity at the same time. Techniques used at present to determine the carrier profile inside NWs show low sensitivity or insufficient spatial resolution. 2-5 By contrast, scanning spreading resistance microscopy (SSRM) has shown the capability of measuring the 2D-carrier distribution with high spatial resolution, high sensitivity and high quantification accuracy on planar MOS structures 6,7 as well as silicon (Si) NWs. 8,9 In this paper we extend this initial work towards the quantitative analysis of the 2D-distribution of carriers in fully-integrated Si NW-based TFETs. EXPERIMENTAL DETAILS Investigated device structures The device structures used in this study resemble NW-based vertical p-i-n diodes and are fabricated using a top-down approach as reported elsewhere in more detail. 10 The gate electrode consists of a wrap-around high- /metal gate configuration. The NW top sections are doped using Mater. Res. Soc. Symp. Proc. Vol. 1258 © 2010 Materials Research Society 1258-P06-02