PSYCHOLOGY AND EDUCATION (2021) 58(2): 813-823 An Interdisciplinary Journal Article Received: 16th October, 2020; Article Revised: 30th December, 2020; Article Accepted: 08th January, 2021 813 www.psychologyandeducation.net QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology Swarup Sarkar 1 , Rupsa Roy 2 1,2 Department of ECE, Sikkim Manipal Institute of Technology Sikkim Manipal University, Sikkim, India. Email: swarup.s@smit.smu.edu.in 1 , rupsa_202010004@smit.smu.edu.in 2 _______________________________________________________________________________________________ ABSTRACT An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, can be optimized by “QCA” nano technology with electro-spin criterion and this technology also supports reversible logic in multilayer 3D platform with less complexity. This paper, primarily presents two novel “QCA” based 3-layered “Adder- Subtractor” designs using the collaboration of multilayer inverter gates, reversible modified 3-input Feynman-Gate and 3-input MG (Majority Gate) with very less cell-complexity, area-occupation, delay and energy-dissipation and high output-strength, temperature-tolerance and accuracy. A clear parametric investigation on presented designs are shown clearly in this paper through a comparative manner with some previous published related structures. Additionally, another parametric-experiment on a novel multibit reversible multilayer “QCA” based “Full-Adder-Subtractor” circuitry using the working phenomenon of “Ripple Carry Adder” (RCA) and multibit subtractor (“ripple borrow subtractor” or RBS) is presented in this proposed work in a proper way and this combination of RCA and multibit subtraction operation converts the proposed circuitry into a hybrid form, which is more effective compare to some other advanced adders in parametric-optimization field. Keyword Electro-Spin, Hybrid, QCA, Reversibility, Ripple Carry Adder, Ripple Borrow Subtractor _______________________________________________________________________________________________ Introduction In this advance nano-technical digital world ALU or “Arithmetic and Logic Unit” is a key component of any processor and Full-Adder is an important component of ALU [8] as a part of the arithmetic unit. Design a novel advanced circuitry of this full-adder with the addition of full-subtractor is the main motive of this paper. Till now, “CMOS Technology” is used to design this proposed circuitry, because this technology effectively follows “Moore’s Law” [1] to design high dense integrated-circuit and according to this law the number of used transistors in a dense integrated- circuit is doubled for every two tears. But, when the area is reduced of these highly dense integrated-circuits, there are several limitations take place, such as design-complexity increment, delay increment due to this complexity, energy- dissipation increment due high leakage current flow etc. Thus, the requirement of an advance low-power, high speed nano-technology becomes very important and proposed “QCA” technology [3-5] with electro-spin criterion can fulfill all these above requirements at the time of any logical device implementation, which is introduced by Tougaw and Lent et.al in 1993 [2]. After that time, various types of combinational and sequential representations are experimented in this “QCA” platform till now. There are also various types of “QCA” based designs on full-adder, full- subtractor or full-adder-subtractor are already published in different articles in different years [9-15] and the parametric- optimization of proposed component is rapidly increased in last few years. In 2017, Barughi and Heikalabad presented a “Full Adder/Subtractor” design using 90 quantum cells in a multilayer 3D platform, where 3 layers are required with 0.6 μm 2 area and 1.5 clock-cycle delay [11] and this occupied area (0.14 μm 2 ) and delay (1.25 clock-cycle) are reduced by Firdous Ahmad et.al in the next year, where the reversible gates (3:3 New Reversible Gate and Modified Feynman Gate) are used to design the published structure with proper power- dissipation calculation. But, in that design the quantum cell number is increased up to 121 cells in single layer “QCA” platform [12]. To minimize this problem, two different structures of full adder and subtractor are formed by Md. Abdullah-Al-Shafi et.al [13], which are published after 3 months of the previous work acceptance. If those two designs are combined in a multilayer platform, then only 49 cells are required to design the “Adder-Subtractor” device with 2 clock-zone latency and 0.04 μm 2 occupied area. In our proposed full-adder-subtractor design, the device-occupied- area, delay, energy-dissipation and quantum-cost are