IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 9, SEPTEMBER 2014 3223
Area and Energy Efficient High-Performance ZnO
Wavy Channel Thin-Film Transistor
Amir N. Hanna, Student Member, IEEE, Mohamed T. Ghoneim, Student Member, IEEE, Rabab R. Bahabry,
Aftab M. Hussain, Student Member, IEEE, Hossain M. Fahad, Student Member, IEEE, and
Muhammad M. Hussain, Senior Member, IEEE
Abstract—Increased output current while maintaining low
power consumption in thin-film transistors (TFTs) is essential
for future generation large-area high-resolution displays. Here,
we show wavy channel (WC) architecture in TFT that allows the
expansion of the transistor width in the direction perpendicular
to the substrate through integrating continuous fin features on
the underlying substrate. This architecture enables expanding
the TFT width without consuming any additional chip area, thus
enabling increased performance while maintaining the real estate
integrity. The experimental WCTFTs show a linear increase
in output current as a function of number of fins per device
resulting in 3.5× increase in output current when compared with
planar counterparts that consume the same chip area. The new
architecture also allows tuning the threshold voltage as a function
of the number of fin features included in the device, as threshold
voltage linearly decreased from 6.8 V for planar device to 2.6 V
for WC devices with 32 fins. This makes the new architecture
more power efficient as lower operation voltages could be used
for WC devices compared with planar counterparts. It was also
found that field effect mobility linearly increases with the number
of fins included in the device, showing almost 1.8× enhancements
in the field effect mobility than that of the planar counterparts.
This can be attributed to higher electric field in the channel due
to the fin architecture and threshold voltage shift.
Index Terms—Area efficiency, device width, performance, thin
film transistors (TFTs), threshold voltage, wavy.
I. I NTRODUCTION
S
EMICONDUCTOR industries are actively exploring
amorphous oxide semiconductors (AOS) as channel mate-
rial in thin-film transistors (TFTs) for high resolution display
technology as they exhibit high mobility, transparency, low-
temperature deposition possibility, and potential integration
opportunity on plastic-based flexible substrates [1]–[3]. This
is especially the case, as the performance of AOS-based
Manuscript received September 10, 2013; revised November 9, 2013,
December 29, 2013, January 25, 2014, and March 4, 2014; accepted June 29,
2014. Date of publication August 5, 2014; date of current version August 19,
2014. This work was supported by the King Abdullah University of Science
and Technology, Thuwal, Saudi Arabia, through the Office of Competitive
Research Funds under Grant CRG-1-2012-HUS-008. The review of this paper
was arranged by Editor H.-S. Tae.
The authors are with the Integrated Nanotechnology Laboratory,
Division of Electrical Engineering, Computer Electrical Mathe-
matical Science and Engineering, King Abdullah University of
Science and Technology, Thuwal 23955-6900, Saudi Arabia (e-mail:
amir.hanna@kaust.edu.sa; mohamed.ghoneim@kaust.edu.sa; rabab.bahabry@
kaust.edu.sa; aftab.hussain@kaust.edu.sa; hossain.fahad@kaust.edu.sa;
muhammadmustafa.hussain@kaust.edu.sa).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2336863
TFTs approach those of the more well-established polycrys-
talline silicon [4]. In addition, the recent need for large-
area high-resolution displays has inspired research on both
material selection as well as device architecture for optimiz-
ing performance of oxide-based TFTs [5]. Large-area high-
resolution displays require both scaling down of the pixel size
to achieve the required resolution, as well as operating the
display device at higher switching speeds to achieve seamless
display experience. This practice in turn necessitates scaling
down the backplane TFT device size as well as searching
for materials with higher intrinsic mobility to achieve higher
output current and faster switching behavior. This is shown
from the transistor output current dependence, under high drain
bias
I
D
=
W
2 L
μ
sat
C
ox
(V
GS
- V
T
)
2
(1)
where μ
sat
is the saturation field effect mobility, W is the
device width, L is the gate length, and C
ox
is gate oxide
capacitance; V
GS
and V
T
are the gate to source bias voltage,
and threshold voltage, respectively. While increasing operation
voltage, V
dd
and hence V
GS
would lead to increased output
current, it would equally increase power consumption that is
quadratically proportional to operation voltage, P αV
2
dd
. This
is not desirable for energy efficient applications, such as use of
light-emitting diode (LED)-based displays for mobile devices,
where power consumption is a key element. Therefore, to opti-
mize TFT performance from device architecture perspective,
device designs that allow smaller gate length ( L ) or larger
device width (W ) need to be explored. New architectures,
however, should be compatible with the downscaling trend of
TFTs, thus not compromising the real estate integrity. Scaling
down TFTs as a method of increasing the output current has
been explored by decreasing the TFT gate length ( L ) through
nonplanar vertical channel architecture, where L is not limited
by lithographic limits. This is usually accomplished using
multigate FET device architecture, which is an improvement
similar to state-of-the-art CMOS technology [6]. However,
it comes at the expense of fabrication cost related requirement
of advanced lithographic technique as well as suffering from
short-channel effects [7].
We have recently shown the effectiveness of wavy chan-
nel (WC) architecture for high-performance transistors and
potential usefulness for TFT applications [8]–[10]. Here,
we show a new TFT architecture that allows the expansion
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