This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE JOURNAL OF SOLID-STATE CIRCUITS 1 A 12-bit 300-MS/s SAR ADC With Inverter-Based Preampliﬁer and Common-Mode-Regulation DAC in 14-nm CMOS FinFET Danny Luu , Student Member, IEEE, Lukas Kull , Senior Member, IEEE, Thomas Toiﬂ , Senior Member, IEEE , Christian Menolﬁ, Member, IEEE, Matthias Brändli, Pier Andrea Francese, Senior Member, IEEE, Thomas Morf , Senior Member, IEEE, Marcel Kossel, Senior Member, IEEE, Hazar Yueksel , Member, IEEE, Alessandro Cevrero, Member, IEEE, Ilter Ozkaya , Student Member, IEEE, and Qiuting Huang, Fellow, IEEE Abstract—A single-channel 12-bit SAR ADC achieving 250–340 MS/s and consuming 4.8–8.0 mW from 0.75 to 0.9 V is presented. At 300 MS/s, the ADC exhibits 61.6-dB peak SNDR and reaches 60.5-dB SNDR and 78.7-dB SFDR with 0.8-V pp, diff input amplitude at Nyquist. It consumes 7.0 mW from a single 0.85-V supply, where 3.7 mW is contributed by the reference buffer. The key element is a comparator with an inverter-based preampliﬁer to achieve low-noise performance with below 1-V pp, diff input amplitude. The common-mode (CM) sensitivity of the inverter is counteracted by an SAR-based CM regulation (CMREG). The regulation adjusts the sampled CM to the optimal CM for the maximum inverter gain using a second capacitive DAC. It adjusts the CM on a sample-by-sample basis and, thus, can correct time-varying CM. The implemented CMREG maintains SNDR above 60 dB for a differential input amplitude mismatch of up to 2 dB or a phase mismatch of up to 15 ◦ . Index Terms— 14-nm CMOS FinFET common-mode- regulation (CMREG) DAC, inverter ampliﬁer, SAR ADC, SAR-based common-mode (CM) rejection. I. I NTRODUCTION T ECHNOLOGY scaling helps drive SAR ADCs to higher conversion speeds thanks to their primarily digital nature. The decreased supply voltage of modern technologies, how- ever, makes it challenging to design highly linear ampliﬁers with high bandwidths. Without ampliﬁcation, the noise of a low-power comparator limits the effective resolution when the Manuscript received March 27, 2018; revised June 1, 2018 and July 16, 2018; accepted July 17, 2018. This paper was approved by Associate Editor Jeffrey Gealow. (Corresponding author: Danny Luu.) D. Luu is with IBM Research Zurich, 8803 Rüschlikon, Switzerland, and also with ETH Zurich, 8092 Zürich, Switzerland (e-mail: luu@zurich.ibm.com). L. Kull, T. Toiﬂ, C. Menolﬁ, M. Brändli, P. A. Francese, T. Morf, M. Kossel, A. Cevrero, and I. Ozkaya are with IBM Research Zurich, 8803 Rüschlikon, Switzerland. H. Yueksel was with IBM Research Zurich, 8803 Rüschlikon, Switzerland. He is now with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598 USA. Q. Huang is with ETH Zurich, 8092 Zürich, Switzerland. Color versions of one or more of the ﬁgures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identiﬁer 10.1109/JSSC.2018.2862890 input amplitude is below 1 V pp,diff . Inverter-based ampliﬁers have been a popular choice in recent designs [1]–[6], because they operate at high current efﬁciencies. Modern CMOS technologies are optimized for performance and area efﬁ- ciency of digital circuits. This makes inverter-based ampliﬁers well suited for low-voltage and low-power ADCs in scaled CMOS. As the transconductances of the NMOS and PMOS are combined, they achieve high gain and excellent power efﬁciency with limited transistor stacking. However, their disadvantages are a higher common-mode (CM) sensitivity and lower linearity than a current-mode logic buffer. Fig. 1(a) shows a pseudo-differential ampliﬁer using two inverter structures. It achieves a high gain when the CM voltage is close to the trip-point voltage, i.e., where the PMOS and NMOS have the same strength. The ampliﬁer is biased to its trip-point voltage when input and output are shorted together. As it is a pseudo-differential circuit, there is no CM rejection, and the CM gain is equal to the differential gain. Fig. 1(b) modiﬁes the circuit to add CM feedback (CMFB) similar to [1]. The two resistors enable sensing of the output CM voltage V out ,cm . This voltage is used to bias the two tail transistors. When the output CM increases, the P-side transistor strengths are reduced and the CM is reduced. In [1], the CMFB is achieved using an additional operational ampli- ﬁer. This results in high CM rejection with added complexity and power consumption. A similar circuit that adds the CMFB is shown in Fig. 1(c) [2], which connects the differential outputs directly to the tail transistors. In this way, large area-consuming resistors can be avoided. However, using two resistors instead of connecting the output directly to the tail transistors results in a lower capacitive output load and allows higher bandwidths to be achieved. Parasitic capacitance on V out ,cm affects only the CM gain bandwidth but not the differential gain bandwidth. Inverter-based ampliﬁers have been used as ring ampli- ﬁers for closed-loop residue ampliﬁcation in pipelined ADCs [4]–[6], as an open-loop residue ampliﬁer in a pipelined SAR ADC [2] or a preampliﬁer in an SAR ADC [1]. Pipelined ADCs require a well-deﬁned, stable, and linear 0018-9200 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.