Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs Giacomo Garegnani, Vincent Fiori ⁎, Gilles Gouget, Frederic Monsieur, Clement Tavernier STMicroelectronics, 850 rue Jean Monnet, F-38926 Crolles, France abstract article info Article history: Received 9 November 2015 Received in revised form 4 March 2016 Accepted 5 March 2016 Available online 8 June 2016 We present an experimental technique and a Finite Element thermal simulation for the determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self-heating. We evaluate the temperature elevation in two steps, as we calibrate the gate resistance over temperature with the transistor at off state at a first stage, and then we deduce the temperature elevation through gate resistance measurements. We simulate the self-heating phenomena in a Finite Elements Method (FEM) environment, both with 2D and 3D models. In order to set up the simulations, we weight the effects of several parameters, such as thermal material properties, the modeling of heat generation and a careful setting of boundary conditions. We present typical temperature fields and local heat fluxes, thus giving concrete indications for solving thermal reliability issues. Simulation re- sults show temperature elevations up to approximately 120 K in the hot spot, 70 K in the gate and 7 K in the Back End of Line (BEoL). The 3D model gives results that are satisfying over the whole set of MOSFETs we consider in this work. Temperature elevation strongly depends on physical dimensions, where transistors endowed with shorter gates suffer from more severe self-heating. We propose a simplified model based on geometrical param- eters that predict maximum and gate temperatures, obtaining satisfying results. Since correlation with measure- ments confirms the correctness of our model, we believe that our simulations could be a useful tool to determine accurate reliability rules and in a context of thermal aware design. © 2016 Published by Elsevier Ltd. Keywords: Nano-scale MOSFETs Self-heating Temperature measurements FEM simulations Correlation analysis Thermal sensors 1. Introduction Downscaling of MOSFETs characteristic size to 28 nm leads to severe self-heating issues [1,2]. Moreover, the Buried Oxide (BOX) in SOI tech- nology guarantees good electric performances but has the drawback of increasing thermal isolation of the active region, causing a more rele- vant temperature increase than in bulk transistors [3–6]. Several studies have been published about the self-heating of nanometer-scaled tran- sistors, presenting Technology Computer Aided Design (TCAD) and mo- lecular dynamics simulations that allow predicting the temperature distribution at a local level. Other studies exploit similar approaches to predict the temperature of FinFETs [2], for which the thermal confine- ment is a critical issue. The common features of those publications are exhaustive analyses of materials' thermal properties [3,7,8], placement of the heat source [1,6], boundary condition settings [4] and heat flux through metal lines in the Back End of Line (BEoL) [9]. Even though a wide range of sophisticated electro-thermal coupled simulations have been built [3,6], in order to produce accurate simulations of thermal phenomena in SOI MOSFETs, we believe that a real effort of correlating simulation results with experimental measures at local level is currently lacking in the self-heating literature. It is therefore our purpose to mea- sure experimentally the temperature elevation in SOI MOSFETs featured by different physical dimensions. In particular, we test transistors with four different gate lengths L (30, 60, 90, 200 nm) and four different depths of the active zone W (0.5, 2, 5, 10 μm) combining those measures in all possible manners, thus obtaining results for sixteen different structures. In this way, a complete understanding of the dependence of self-heating phenomena on the physical dimension of the transistor is retrieved. Then, we set up a FEM steady-state thermal simulation to compute the temperature field in the whole structure. Besides comput- ing the location and value of the hot spot of the MOSFET, the simulation results allow to predict the heat fluxes in a wafer level configuration, as well as the temperature gradients. Moreover, we extract the value of the average temperature of the gate in order to verify the correlation of FEM results with measurements, thus validating our analysis. Since the cor- relation of simulations and measurements is promising, we believe that the model we present in this work could be exploited as a tool for careful material selection and in general for thermal aware design, eventually improving overall thermal reliability of SOI devices. We will base our future work on this simulation, verifying the thermal be- havior of MOSFETs in different packaging techniques, such as flip-chip and wire bonding, as well as the impact of the BOX thickness and the temperature distribution in metal interconnects. The structure of our Microelectronics Reliability 63 (2016) 90–96 ⁎ Corresponding author. E-mail address: vincent.fiori@st.com (V. Fiori). http://dx.doi.org/10.1016/j.microrel.2016.03.007 0026-2714/© 2016 Published by Elsevier Ltd. Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr