Indonesian Journal of Electrical Engineering and Computer Science Vol. 25, No. 2, February 2022, pp. 805~813 ISSN: 2502-4752, DOI: 10.11591/ijeecs.v25.i2.pp805-813  805 Journal homepage: http://ijeecs.iaescore.com Low power architecture of logic gates using adiabatic techniques Minakshi Sanadhya, Devendra Kumar Sharma Department of Electronics and Communication Engineering, Faculty of Engineering and Technology, SRM Institute of Science and Technology, Ghaziabad, India Article Info ABSTRACT Article history: Received Aug 18, 2021 Revised Nov 23, 2021 Accepted Dec 3, 2021 The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for power- dissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively. Keywords: Adiabatic techniques Delay Logic gates Performance analysis Power dissipation Rise time This is an open access article under the CC BY-SA license. Corresponding Author: Minakshi Sanadhya Department of Electronics and Communication Engineering, Faculty of Engineering and Technology SRM Institute of Science and Technology NCR Campus, Ghaziabad, Uttar Pradesh, India Email: minakshisandhya@gmail.com 1. INTRODUCTION Energy consumption is a crucial parameter in ultra large scale integration (ULSI) technology. Presently, many electronic devices are portable, compact and show high performance. The reduction in power dissipation is the most important factor for achieving higher performance with high density. In complementary metaloxide semiconductor (CMOS) circuits, several new approaches are emerging to achieve low power consumption. When timing requirement is not crucial, adiabatic logic is the most outstanding approach amidst the various techniques to lessen the power consumption in CMOS circuits [1]. Adiabatic logic suggests the make use of a trapezoidal power clock that permits charging or discharging at a steady current without current flow. Therefore, lesser amount of energy is dissipated by adiabatic circuits [2]. Adiabatic logic works on alternating current supplies instead of direct current, which makes the recycling of energy in the circuit [3]. Adiabatic logic is a unique technique for creating logical circuits that assures exceptional density and very less power consumption. Bennett first proposed this technique in 1992 and declared that the energy