2600 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 5, OCTOBER 2009 Time Determination of BGO-APD Detectors by Digital Signal Processing for Positron Emission Tomography Jean-Daniel Leroux, Student Member, IEEE, Jean-Pierre Martin, Member, IEEE, Daniel Rouleau, Catherine M. Pepin, Jules Cadorette, Réjean Fontaine, Senior Member, IEEE, and Roger Lecomte, Member, IEEE Abstract—Coincidence timing resolution in Positron Emission Tomography (PET) can be improved by replacing fast analog pulse shaping and Constant Fraction Discriminator (CFD) with fully digital signal processing. This can be achieved by digitizing the signal from individual detectors using 100-MHz, 8-bit Analog-to-Digital converters (ADC) and by processing the data on-the-fly in Field Programmable Gate Arrays (FPGA). Various digital filters and baseline restorers were implemented and combined with numerical least mean square fit to the data to extract the time of interaction and the energy deposited in BGO-APD detectors. An intrinsic time resolution of 7.2 ns was obtained with digital techniques. However, it is shown that bias in the timestamp estimation can be introduced by digital time discrimination techniques, which could affect the ability of digital methods to accurately estimate random event rates by the delayed time window method. Accordingly, the coincidence FWHM metric should not be the only figure of merit when comparing digital and analog time discrimination strategies. Index Terms—Avalanche photodiodes, digital circuits, digital signal processing, field-programmable gate arrays (FPGAs), numerical methods, PET, time resolution. I. INTRODUCTION T HE EVER increasing use of small animal models in PET imaging requires improvement of spatial resolution, re- duction of parallax error by depth-of-interaction measurement in detectors, and more accurate selection of useful events to im- prove image quality [1], [2]. A related goal would be the ability to reconfigure system parameters according to the imaging pro- tocol. In another respect, it could be advantageous to be able to adapt the system to the novel scintillation detectors that are be- coming available, rather than redesign the front-end processing Manuscript received June 17, 2008; revised February 02, 2009. Current ver- sion published October 07, 2009. This work was supported in part by the Natural Sciences and Engineering Research Council of Canada (NSERC), the Fonds Québécois de Recherche sur la Nature et les Technologies (FQRNT), and the Canadian Institutes of Health Research (CIHR). J.-D. Leroux and R. Fontaine are with the Department of Electrical Engi- neering and Computer Science, Université de Sherbrooke, Sherbrooke, QC J1K 2R1, Canada (e-mail: j-d.leroux@usherbrooke.ca) J.-P. Martin is with the Department of Physics, Université de Montréal, Mon- tréal, QC H3C 3J7, Canada. D. Rouleau, C. M. Pepin, J. Cadorette, and R. Lecomte are with the Depart- ment of Nuclear Medicine and Radiobiology, Université de Sherbrooke, Sher- brooke, QC J1K 2R1, Canada. Digital Object Identifier 10.1109/TNS.2009.2023655 Fig. 1. Schematics of digital signal processing unit for one BGO-APD detector implemented in a FPGA. Event data are sent to another unit for further pro- cessing and coincidence verification. electronics. To address many of these problems, it has been pro- posed to replace the analog processing electronics of PET scan- ners by a fully digital, programmable, system architecture al- lowing maximum flexibility and upgradeability [3], [4]. Various numerical algorithms to extract the time of occur- rence and the amplitude of signals generated by BGO/APD de- tector modules [5] were proposed in [6]. In this work, these al- gorithms were revisited and new considerations with respect to the timestamp bias that may be introduced by digital time dis- crimination techniques have been investigated. Whereas several other works have been dealing with digital time discrimination methods recently [7]–[15], none has really addressed this issue. II. SYSTEM ARCHITECTURE In the initial implementation of the digital system archi- tecture [4], the signals were digitized directly at the output of each Charge Sensitive Preamplifier (CSP) connected to an APD-based detector without further shaping or anti-aliasing filtering in order to preserve maximum signal information. Digitized data were fed to a Field Programmable Gate Array (FPGA) programmed to extract relevant information from the signal waveform. A simplified scheme of the acquisition and processing blocks is shown in Fig. 1. The digital output from the free-running ADC is continuously stored in circular RAM until a signal with energy above a pre- determined threshold is detected. As soon as this condition is satisfied, a time stamp is latched from a 100 MHz global clock synchronized with all other FPGAs in the system and a state 0018-9499/$26.00 © 2009 IEEE