1 Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization Gracieli Posser, Student Member, IEEE, Vivek Mishra, Student Member, IEEE, Palkesh Jain, Member, IEEE, Ricardo Reis, Senior Member, IEEE, and Sachin S. Sapatnekar, Fellow, IEEE Abstract—Electromigration (EM) in on-chip metal inter- connects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient charac- terization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently considerably reducing the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved about 2.5×-161× by avoiding the EM-critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications. Index Terms—Electromigration, Cell-internal Signal Electro- migration, Joule Heating, Current Divergence, Physical Design, EDA. I. I NTRODUCTION Electromigration (EM) is a major source of failure in on- chip wires and vias, and is becoming a progressively increas- ing concern as feature sizes shrink [1]. EM is initiated by current flow through metal wires and may cause open-circuit failures over time in copper interconnects. Traditionally, EM has been a significant concern in global power delivery networks, which largely experience unidirec- tional current flow. Recently, two new issues have emerged. First, EM analysis can no longer be restricted just to global wires. Traditional EM analysis has focused on higher metal layers, but with shrinking wire dimensions and increasing currents, the current densities in lower metal layers are also now in the range where EM effects are manifested. EM effects are visible at current densities of about 1MA/cm 2 , and such current densities are seen in the internal metal wires of standard cells, resulting in cell-internal signal EM [2]. These high current densities arise because local interconnect wires within standard cells typically use low wire widths Manuscript received October 29, 2014; revised April 13, 2015; accepted June 8, 2015. This work was supported in part by SRC 2012-TJ-2234, Brazilian National Council for Scientific and Technological Development (CNPq - Brazil) and Coordination for the Improvement of Higher Education Personnel (CAPES). Gracieli Posser and Ricardo Reis are with the Universidade Federal do Rio Grande do Sul - PPGC/PGMicro, Porto Alegre, 91501-970 Brazil (e-mail: gposser@inf.ufrgs.br; reis@inf.ufrgs.br). Vivek Mishra and Sachin S. Sapatnekar are with the University of Min- nesota, ECE Department, Minneapolis, MN, USA (e-mail: vivek@umn.edu; sachin@umn.edu). Palkesh Jain is with Qualcomm India, Bangalore, India (e-mail: palkesh@qti.qualcomm.com). to ensure compact cell layouts. In short metal wires, such effects were traditionally thought to be offset by Blech length considerations, but for reasons discussed later, such effects do not help protect intra-cell wires in designs at deeply scaled technology nodes. Second, EM has become increasingly important in signal wires, where the direction of current flow is bidirectional. This is due to increased current densities, whose impact on EM is amplified by Joule heating effects [3], since EM depends exponentially on temperature. Therefore, the current that flows through these wires to charge/discharge the output load can be large enough to create significant EM effects over the lifetime of the chip. Intra-cell power networks are also associated with EM concerns. In going down to deeply scaled technology nodes, the current through the power rails of the cells has remained roughly constant while the cross-sectional area of power rails has decreased, causing the current density in power rails to in- crease [4]. Moreover, the power rails are generally subjected to a unidirectional current flow, referred as DC electromigration, which acts more aggressively in causing electromigration [5]. In the cell library used in this work, we can see high current densities on the Vdd and Vss power rails as well as on signal wires, reducing the lifetime of the cells. For example, we compute signal wires in an INV X4 cell to have an effective average current density of 1.8 MA/cm 2 at 2GHz, while power wires have an effective current density of 2.15 MA/cm 2 in a 22nm technology. This switching rate is very realistic, and can be seen in, for example, clock buffers in almost any modern design. While the cell-internal signal EM problem has been de- scribed in industry publications such as [2], its efficient analysis is an open problem. In this work 1 , we study the problem of systematically analyzing cell-internal signal EM due to both AC EM on signal wires and DC EM on the Vdd and Vss rails of the cells. We devise a solution that facilitates the analysis and optimization of cell-internal signal EM for a standard cell library based design. We first develop an approach to efficiently characterize cell-internal EM over all output, Vdd, and Vss pin locations within a cell, incorporating Joule heating effects into our analysis. We then formulate the pin optimization problem that chooses cell output pins during place-and-route so as to maximize the design lifetime. We motivate the problem using the INV X4 (inverter with size 4) cell, shown in Fig. 1(a), from the 45nm NANGATE 1 ”A preliminary version of this work was published in [6].” ©2015 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to pubs-permissions@ieee.org.