Impact of the gate-stack change from 40nm node SiON to 28nm High-K Metal Gate on the Hot-Carrier and Bias Temperature damage Alain Bravaix 1 , Y. Mamy Randriamihaja 1,2* 1 IM2NP-ISEN, UMR CNRS 7334, Maison des technologies, Place G. Pompidou, 83000 Toulon - France phone: (+33) 494038992, alain.bravaix@isen.fr V. Huard 2 , D. Angot 2 , X. Federspiel 2 , W. Arfaoui 1,2 , P. Mora 2 , F. Cacho 2 , M. Saliva 1,2 C. Besset 2 , S. Renard 2 , D. Roy 2 , E. Vincent 2 2 STMicroelectronics, Crolles 2 alliance, 850 rue Jean Monnet, 38926 Crolles, France * now at Globalfoundries, Tech. Development division, 400 Stonebreak ext. road Malta, NY, 12020, USA Abstract— High-K Metal-Gate 28nm node (C28) with equivalent gate-oxide thickness EOT= 1.35nm has been compared to low power 40nm CMOS node (1.7nm) on silicon bulk. Hot-Carrier damage in C28 originates from the same permanent ΔN IT mechanism under current driven Multiple Particle (MP) interactions, relative to the SiON interface layer while border to bulk oxide traps make the larger difference between NMOS and PMOS transistors. This has been obtained by their respective temperature activation and AC response behaviors at Room Temperature and High Temperature due to the distinct proportion of accessible shallow/deep defects in the HK-MG structures. Keywords: Hot-Carrier, Bias Temperature damage, Phonon mode, Multivibrational excitation, H-bond breaking rate I. INTRODUCTION Great attention has to be paid to determine the Hot-Carrier (HC) resistance and Bias Temperature (BT) effects in last CMOS nodes optimized for high performance and low power (LP) consumption, facing the modification of the gate-stack from SiON to high-K metal gate (HK-MG) processing [1, 2]. This is related to the contribution of fast and slow traps that can be involved in both structures [2, 3] depending on the interface layer (IL) thickness with respect to the high-K one, and to the presence of deep neutral traps (E’γ) [4] and K N centers [5]. While tremendous efforts have been dealt to the comprehension and impact of BT mechanisms [6, 7], less attention has been paid to HC damage due to the reduction of supply voltage V DD with scaling [8, 9]. However, HC defect generation rate for gate lengths L G < 130nm become related to the number of incident channel carriers [9, 10] in contrast to the smaller amount (uniformly) involved under BT conditions, whereas HC vs. BT represents a significant proportion of the accelerating degradation under digital operation in products at high temperature [11]. We compare in this work NMOS and PMOS HC resistance from the last 28nm CMOS node by comparison of the permanent and recoverable damage using DC and AC stressing. We first assess worst-case DC stressing in section III to determine the basics of acceleration factor degradation. High temperature (HT) stressing is then performed in section IV in order to distinguish the effective temperature activation (E A ) directly. AC stressing is finally used (section V) to characterize the distinct damage mechanisms between IL and bulk oxide through both gate stacks. II. EXPERIMENTS LP 40nm CMOS node with a SiON gate dielectric is compared to HK-MG with TiN stacks on silicon bulk as illustrated in Fig.1. This latter has been optimized in performance using a 1.5nm-thick IL (SiON, ε IL =5.7) close to the 1.7nm-thick HK (HfSiON, ε HK =20) giving EOT=1.35nm in NMOS. For PMOS, a SiGe layer is used in order to gain in current drivability. DC and AC experiments are performed Figure 1. Schematic illustration of the last distinct CMOS structures between LP 40nm SiON and 28nm HK-MG gate stack using IL-SiON (1.5nm thick) and HfSiON (1.7nm). A 10nm SiGe layer is used in PMOS side only (in N-Well). Poly Si SiON 1.7nm n+ n- n- n+ p- p- STI 40nm CMOS node Si p Well n+ n- IL SiON 1.5nm Metal stack p- (SiGe PMOS) n+ n- p- STI 28nm CMOS node Si p Well Hf SiON 1.7nm 978-1-4799-0113-5/$31.00 ©2013 Crown 2D.6.1