An Efficient Mechanism to Provide Full Visibility for Hardware Debugging Wei-Hsiang Cheng, Chin-Lung Chuang, and Chien-Nan Jimmy Liu Department ofElectrical Engineering National Central University, Taiwan, R. 0. C. t92521007, 92541 014}@(4cc.ncu.edu. tw, jimmy@,ee. ncu. edu. tw Abstract - Special hardware such as FPGA can provide In order to solve this problem, a snapshot method was higher simulation speed for verification. However, it is very proposed in [4] that used external memory instead of hard to debug due to the poor visibility of internal nodes. In EMB as the trace buffer. This approach can periodically [4] , a snapshot method was proposed to "record" the "record" the internal behaviors of a FPGA and "replay" a internal behaviors of an FPGA and "replay" a certain certain period of time in a software simulator to obtain period of time in a software simulator. In the snapshot full visibility for debugging. Because there are many approach, we can still keep a high simulation speed with a powerful tools for software simulators, debugging using better debugging environment. Although saving the values of this approach will become much easier than using watch all internal registers is a sufficient solution to reconstruct the simulation waveform, it is not the optimal solution for large pints or ELA only Mostimporant as iusatin designs. In this paper, we propose a method to reduce the Figur 1 this appoach canustill haveh simulatin number of recorded registers in the snapshot approach. Our sPeed becaue simulation rus aremfinished in experiments have shown that both hardware overhead and FPGA. Software simulators only run a small period of storage data can be greatly reduced by our approach, which time assigned by users, such as the time window 3000 in enables the snapshot method to be applied on larger designs. Figure 1, to debug their designs with full visibility. I. INTRODUCTION Emulation time _ Up to now, logic simulators have been the most _JL-JL_JL_IL_ JL_IL_ L- L popular verification tools. Both hardware designs and test F r r bench are put together in the virtual environment A-1 constructed using software only. Therefore, users can have full controllability and observability during the verification process. Once an error occurs at the outputs, 1 2 3 4 5--- 300s this feature allows users to trace into the designs and find \ t ------ - the bugs easily in the debugging process. However, Snapshot per 000 cycles BUG especially for modern complex designs, we often require a huge number of input patterns to verify the complex Figure 1 Whole simulation process to find the bug. [4] system's behaviors. In this situation, software simulation In that approach [4] , we record the values of all is often too slow (about IKHz to 10KHz) to verify all internal flip-flops and primary inputs because those input patterns. values are enough to reconstruct the whole simulation In order to accelerate the speed to verify large numbers waveforms. Although selecting all internal registers is a of input patterns, a hardware emulator [1] is often used at sufficient solution to reconstruct the simulation waveform, the final stage of verification. However, the cost of an it is not the optimal solution for large designs. In this entry-level emulator could be as much as one million US paper, we propose a method to translate the node dollars, which is not affordable for typical products. selection problem into the minimum costfeedback vertex Compared to hardware emulators, FPGAs have quite set (MCFVS) [5] problem and then use existing reasonable prices and high running speed. However, it is algorithms to obtain a minimum selection of internal very hard to debug the designs due to the poor visibility registers to be recorded. As shown in the experimental in FPGAs. FPGA vendors have also noticed this problem. results, the storage data and hardware overhead can be Therefore, they provide an Embedded Logic Analyzer significantly reduced, which enables the snapshot method (ELA), such as Signal Tap II [2] or Chip Scope Pro [3] , to be applied on more realistic designs. to watch internal signals. However depending on the The remainder of this paper is organized as follows. In capacity of the embedded memory block (EMB), ELA Section II, the original snapshot method is briefly has only a limited number of channels and sample-depth introduced. The proposed method for reducing storage for capturing signals. data is discussed in Section III. The experimental results are demonstrated in Section IV. Finally, some conclusions This work was supported in part by R 0 C. Nationai Science Councii under Grant are summarized in Section V. NSC93-2220-E-008-007 . 0-7803-9390-2/06/$20.00 ©2006 IEEE 811 ISCAS 2006