Hybrid Testbench Acceleration for Reducing Communication Overhead Chin-Lung Chuang and Chien-Nan (Jimmy) Liu National Central University MORE THAN 70% of the design effort today is in verification, suggesting that there is considerable room for improvement in the traditional verification flow. Software simulators typically put both the test- bench and the design under test (DUT) into the same software environment, which is a popular tech- nique for discovering functional bugs in early design stages. Although design sizes have swiftly reached multimillions of gates, software simulation speed (about 1 KHz to 10 KHz) is not sufficient to ade- quately test all possible bugs. For large designs, hard- ware emulation is sometimes used instead of software simulation. The hardware emulation process synthe- sizes the DUT in the emulator and cooperatively works with the target board, firmware, software, and operating system to perform comprehensive system verification. Typically, hardware emulation enables several orders-of-magnitude performance improvement in simulation speed (about 1 MHz to 50 MHz). However, because of the high cost of hardware emulation, hardware-assisted simulation acceleration is often used as a trade-off for the functional verification that cannot be achieved with slow software simulation alone. In this article, we describe a new approach, hy- brid embedded testbench acceleration (HETA), that we have developed to reduce the communication overhead in hardware accelerators. HETA is based on a simple embedded CPU plus spe- cial hardware. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator with only 0.57% hardware overhead. Background and motivation In response to the increasing demand for hardware- assisted simulation acceleration, some vendors have proposed solutions using signal-based acceleration. As Figure 1a shows, the concept behind signal- based acceleration is to retain the testbench in soft- ware simulation and put the DUT into hardware to obtain more speedup at a lower cost. Because only the testbench remains in the slow software sim- ulation, the overall simulation is expected to have a greatly improved speedup. Unexpectedly, the com- munication overhead between the software simula- tor and hardware accelerator dominates the overall speedup. Because the software testbench and hard- ware DUT must synchronize with each other at every clock cycle, signal-based acceleration offers only limited speed improvement, around 10 that of software simulation. For example, to reduce the communication overhead, Accellera has proposed the Standard Co-Emulation Modeling Interface (SCE-MI), 1 which upgrades signal-based acceleration to transaction- based acceleration (TBA), as Figure 1b shows. TBA requires designers to describe the transactor in a synthesizable fashion and rewrite the testbench in a high-level language. However, not all test- benches can be translated to the transaction level successfully. Previous results have shown the Hybrid Embedded Testbench Acceleration Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and soft- ware. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelera- tor and with only 0.57% hardware overhead. 0740-7475/11/$26.00  c 2011 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers 40