62 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 23, NO. 1, FEBRUARY 2000 An Analytical Model of Simultaneous Switching Noise in CMOS Systems Hye-Ran Cha and Oh-Kyong Kwon, Member, IEEE Abstract—An accurate and analytical model for simultaneous switching noise (SSN) on ground lines in CMOS circuits is pre- sented. This model can compute SSN for the case where only some drivers switch and the others remain quiet, that is, the model con- siders the loading effects on the quiet drivers. It was confirmed that the proposed model is more accurate than the existing ones through HSPICE simulation using the level 28 model for short- channel MOSFET’s. The proposed model can provide useful de- sign guides for CMOS driver circuits. Index Terms—Active driver, CMOS output buffer, quiet driver, short-channel MOSFET, simultaneous switching noise. I. INTRODUCTION A S THE operation speed of CMOS integrated circuit gets faster, the switching speed and the slew rate of output buffers also need to be increased. And the number of the I/O pins is also increased, as VLSI chips come to provide more compli- cated functions. This trend makes the switching noise on both the power and ground buses more severe, which can result in the performance degradation and even the logic fault. There- fore, much effort to analyze the simultaneous switching noise (SSN) has been made [1]–[4]. In [1] and [2], the authors did not include the negative feedback effects on SSN. Thereafter, Sen- thinathan and Prince [3] calculated SSN considering the effects of negative feedback. In [4], Vaidyanath et al.assumed the linear increase of SSN during the input signal transition time, which is not exactly the case. While Senthinathan, Prince, and Vaidyanath used Shichman–Hodges’ current equation [5] for a MOSFET model, we chose Sakurai’s -power model [6], because the proposed model is for 0.35 μm CMOS circuits and the short-channel effects such as velocity saturation are remarkable in the deep submicron devices. Of course, the analysis of SSN using Sakurai’s -power model has already been reported [7], but when the previous model [7] is applied to the case where some drivers switch and the others remain quiet, it is found that the voltage fluctuations on the power buses are overestimated. In this paper, we present a new model for SSN considering the loading effects on the quiet drivers. The model can calculate the ground bouncing and the voltage fluctuations on the output node of quiet drivers as a function of the effective inductance of ground lines, the number of switching drivers, the rising time of the input signal, the width of transistor of switching drivers, and the load capacitance of quiet drivers. And it is found that Manuscript received January 25, 1999; revised November 5, 1999. The authors are with the Division of Electronic and Electrical Engineering, Hanyang University, Seoul 133-791, Korea (e-mail: okwon7@chollian.net). Publisher Item Identifier S 1521-3323(00)01389-7. the proposed new model is closer to HSPICE simulation results than the previous works [7], [8]. II. APPROACH AND MODELING Consider a typical CMOS chip-to-chip system with capac- itive load, where CMOS off-chip drivers (OCD) are active and the remaining drivers are quiet. All of the active drivers have an input signal which is a ramp signal switching from low to high during , and the input of the quiet drivers, remains static at high. All of the drivers share the ground induc- tance as shown in Fig. 1. Until, various approaches and models have been proposed for analyzing SSN [1]–[5], [7], [8]. However, most of them are interested in cases where all the drivers are active, that is, they switch together at the same time. It is because it is the worst case, where the noise voltage caused by simultaneous switching is largest. Although some approaches assume that some quiet drivers exist, they do not consider the influence of SSN caused by active drivers on the entire circuit operation including the quiet drivers. Yet, in practice it is more likely that some drivers will merely switch, and the other drivers will keep the previous state. The noise voltage can vary depending on whether inactive drivers sharing ground with active drivers exist. In addition, the SSN caused by the active drivers will influence the state of the quiet drivers, which will possibly lead to wrong operation such as logic fault. Therefore, accurate analysis of the situation where only some part of the drivers switch simultaneously, and the influence of SSN on the output node of the quiet drivers is also needed. As shown in Fig. 1, the input of the quiet drivers is high, and their initial output nodes are discharged to 0 V. If drivers switch from low (0 V) to high ( ), the transient current will flow through the inductor during transition, and it will lead to a rise in ground potential according to (1) (1) Such voltage fluctuation on ground lines means that the source potential of NMOS transistors of the quiet drivers becomes higher than the drain potential, the output of the quiet drivers. Consequently, the current flows through each NMOS transistor of the quiet drivers and charges the output capacitor, because NMOS transistors are steadily turned-on at their high input. That is, the potential of the output nodes that must be fixed at 0 V will rise depending on SSN caused by active drivers. On the other hand, if it were not for the 1521-3323/00$10.00 © 2000 IEEE