Investigation of Fabricated Through Glass Via (TGV) Process by Inductively Coupled Plasma Reactive Ion Etching of Quartz Glass Yu-Hsiang Tang * , Yu-Hsin Lin, Tsung-Tao Huang, Jun-Sheng Wang, Ming-Hua Shiao, and Chih-Sheng Yu Instrument Technology Research Center, National Applied Research Laboratories, 300, Taiwan sky520830@narlabs.org.tw Abstract- In this paper, we report the fabrication process of Through Glass Via (TGV) structure and basic design rules for glass based Three-Dimensional Integrated Circuit (3D-IC) packaging as well as a process flow for glass interposer applications. Quartz glass materials have been widely used in many packaging applications for micro electromechanical systems (MEMS), optical devices, and biomedical chips. Our work focuses on a 3D-IC package approach based on the use of thin glass as a substrate material. For through-glass-vias, holes were etched in glass wafers by photolithography and inductively coupled plasma- reactive ion etching (ICP-RIE) technologies and evaluated. The results of fabrication of TGV morphology showed a very good compromise between wafer thickness, TGV shape and via diameter for vertical interposer with 50 µm diameters in 150 µm thin quartz glass wafer still very stable for thin wafer processing without complicated processes. INTRODUCTION Electronic products in recent years are developed to be lightweight, thin, short and small. They are different from the past chip design in two dimensional mode. Through the development of three dimensional (3D) stacking, the connection paths inside chips on different layers can be shortened to increase signal transmission speed and reduce noise and power consumption; simultaneously, this also allows integration of more versatile functions, meeting the future strict requirements by mobile devices for being light, thin and multifunctional [1]. Since 3D-IC technology is an advanced semiconductor manufacturing platform technology, it can be widely used in many electronic products, such as handheld electronic devices (including smart phones, tablet PC), MicroElectroMechanical (MEMS) components, automobile electronic system and biomedical sensing chips etc. As the manufacturing technology is miniaturized to the nanoscale, in response to miniaturization manufacturing technology that generates higher number of signal pins and increases chip complexity, perforation wire technology has received increasing attention. It can shorten the length of metal wire and the electric resistance of connecting wire, and further reduce chip area. It has many features, like small size, high efficiency, low power consumption and low cost. 3D-IC technology is mostly special in that it allows chips of different functions and even different substrates to be made by their best suitable technologies, and then integrated and stacked three- dimensionally by Through Silicon Via (TSV) technology [2]. TSV is the key technology for 3D IC stack chips. The technology uses vertical connection to integrate wafer stacking and achieve electrical conduction among chips. The substrate to connect chips can be made of silicon, glass, metal, and even polymer materials [3]. TSV technology has received increasing emphasis and performs better than metal and polymer materials. However, silicon substrate is limited by cost and electrical insulation. In contrast, glass has the coefficient of thermal expansion (CTE) matching silicon substrate, excellent surface flatness and high resistivity [4]. This study uses quartz glass as substrate material, which has great potential for the development of micro components because it has CTE, piezoelectric property, insulation, light transmission, high hardness matching silicon substrate, as shown in Table 1 [5]. The disadvantage lies in the difficulty when quartz glass is used to make holes of small line width (< 50 m) and high aspect ratio. The biggest bottleneck is the manufacturing difficulty and the charge cumulative effect due to the non- conductive property, causing slow process and poor efficiency. This study researched glass microfabrication technologies for Through Glass Via (TGV) formation can be applied interposer substrate of Three-Dimensional Integrated Circuit (3D-IC) packaging [6]. Nowadays, silicon is a mature material in semiconductor technology, but quartz glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE and most importantly low cost solution [7]. During the design phase of a glass based package, the selection of a suitable glass mainly depends on reliability and process issues. For through-glass-vias, holes were etched in glass wafers by photolithography and inductively coupled plasma-reactive ion etching (ICP-RIE) technologies and evaluated. Presently, TGV etching technology has been studied by many researchers in the area of MEMS. Most literatures indicate ICP-RIE as the major system, which uses metal layer as etching mask to obtain structure of high aspect ratio. In 2002, Li et al. [8] used SF 6 as etching plasma ingredient, on Pyrex glass, to produce perforation structure of diameter 40-80 m and aspect ratio 5-7. The experiment obtained high density perforation conductive structure of line width 50 m and depth 150 m and completed electroforming for nickel metal wire, Proceedings of the 10th IEEE International Conference on Nano/Micro Engineered and Molecular Systems (IEEE-NEMS 2015) Xi’an, China, April 7-11, 2015 978-1-4673-6695-3/15/$31.00 ©2015 IEEE 401