Fast and Energy-Frugal Deterministic Test Through Efficient Compression and Compaction Techniques * Ozgur Sinanoglu and Alex Orailoglu Computer Science and Engineering Department University of California, San Diego La Jolla, CA 92093 {ozgur, alex}@cs.ucsd.edu Abstract Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthermore, the transitions that occur in the scan chains during these shifts reflect into significant levels of circuit switching unnecessarily, increasing the power dissipated. Judicious encoding of the correlation among the test vectors and construction of a test vector through predecessor updates helps reduce not only test application time but also scan chain transitions as well. Such an encoding scheme, which additionally reduces test data volume, can be further enhanced through appropriately ordering and padding of the test cubes given. The experimental results confirm the significant reductions in test application time, test data volume and test power achieved by the proposed compression methodology. 1 Introduction High quality test for a core in a System-On-a-Chip (SOC) design necessitates full controllability of the inputs and full observability of the outputs of the core. The boundary scan scheme is widely used as this access to core I/Os is provided through shift registers which are directly controllable and observable. In this scheme, a flip-flop is connected to each I/O of the core, as illustrated in Figure 1, effectively ensuring the isolation of the core during test; these flip-flops are stitched together into a shift register, controlled from a single pin and observed through another. Even though the test challenge is eased in a scan-based environment, the use of serial shift both for loading the test data into a shift register and for observing the test responses captured in the shift register, necessitates numerous test application cycles, equal approximately to the product of the shift register length and the number of test vectors. In addition to the prolongation in test application time, scan-based testing suffers from increased test power; during shift operations, the frequent transitions in the shift register reflect into rippling at the circuit lines unnecessarily, hence resulting in increased power dissipation. The consequent overheating of the chip during test may in turn result in damaging the chip. Serial shift operations for observing the test responses can be eliminated through utilization of a compaction circuitry; instead of loading the test responses to a shift register and subsequently shifting them out serially, a MISR can be used to compress these responses into a signature, eliminating the necessity for a shift register for the outputs of the core. Yet, reduction in test application time necessitates getting around the serial loading of the test vectors into the shift register; instead, the test vector that already exists in the shift register can be updated to obtain the subsequent test vector by utilizing the correlation between two consecutive test vectors. Information regarding the correlation can be further encoded to enable a scheme wherein this encoded data is loaded into a smaller shift register, a correlation register; this correlation information can then be decoded on-chip to directly update the current test vector and hence obtain the subsequent one. The size of the correlation register, which equals the number of bits in the encoded data, determines the reduction in test application time. * The work of the first author is supported through an IBM graduate fellowship.