Efficient RT-level Fault Diagnosis Methodology Ozgur Sinanoglu and Alex Orailoglu Computer Science and Engineering Department University of California, San Diego La Jolla, CA 92093 ozgur, alex @cs.ucsd.edu ABSTRACT Increasing IC densities necessitate diagnosis methodologies with en- hanced defect locating capabilities. Yet the computational effort ex- pended in extracting diagnostic information and the stringent storage requirements constitute major concerns due to the tremendous number of faults in typical ICs. In this paper, we propose an RT-level diagnosis methodology capable of responding to these challenges. In the pro- posed scheme, diagnostic information is computed on a grouped fault effect basis, enhancing both the storage and the computational aspects. The fault effect grouping criteria are identified based on a module structure analysis, improving the propagation ability of the diagnos- tic information through RT modules. Experimental results show that the proposed methodology provides superior speed-ups and signifi- cant diagnostic information compression at no sacrifice in diagnostic resolution, compared to the existing gate-level diagnosis approaches. 1. INTRODUCTION Diagnosing IC defects is becoming more crucial as increasing chip size and complexity magnify the defect probabilities. Accurate pin- pointing of the cause of the failure based on the defective chip re- sponses yields significant financial benefits, both by ramping up yields rapidly for next generation ICs and by reducing chip returns. The diagnosis process has been traditionally carried out by match- ing the defective chip responses with the precomputed faulty responses. Such a process is performed based on a specific fault model as taking into account any possible defect is apparently infeasible. Attaining certain diagnostic resolution necessitates the selection of a represen- tative fault model; the defective chip behavior is thus attributed to the presence of modeled faults. Currently existing diagnosis methodolo- gies are typically based on the utilization of diagnostic information on a per fault basis; the applicability of these techniques is typically lim- ited by the storage and computational complexity stemming from the tremendous number of possible fault locations in ICs. Two types of fault dictionaries are used in typical gate-level diag- nosis schemes: full fault dictionary and pass-fail dictionary. A full dictionary stores for each test vector and for each fault the complete circuit responses. In the presence of outputs, test vectors and faults, the size of a full fault dictionary is . Although a full dictionary delivers perfect diagnostic resolution, storing only the information regarding whether faults are detected by test vectors in a pass-fail dictionary provides at significantly lower cost almost as high a resolution as a full dictionary. The size of a pass-fail dictionary is still considerable, however, as bits are required. Besides their storage complexity, building these dictionaries demands signifi- cant computational effort due to the tremendous number of faults. In order to reduce the space needed to store a fault dictionary, numerous methods have been proposed [1, 2, 3, 4, 5]; a detailed summary can be The work of the first author is supported through a graduate fellow- ship by IBM. found in [6]. Although these techniques alleviate the storage require- ments slightly, the computational challenges remain yet unsolved. An aspect that promises to cope with the aforementioned storage and computational challenges, yet overlooked by the previous diag- nosis methodologies, is the utilization of RT-level techniques. Hierar- chical approaches have been widely utilized in test generation [7] and fault simulation [8, 9], delivering computational speedups. Utilization of design hierarchy along with the exploitation of module functional- ity helps extract diagnostic information while satisfying storage and computational requirements. The computation of diagnostic information on a per grouped faults basis rather than on a per fault basis attains significant storage com- pression. The utilization of RT module functionalities helps capture the grouped fault effect propagation behavior of the modules, enabling the tracking of the diagnostic information through RT modules. While the computation of diagnostic information regarding grouped fault effects delivers computational efficiency, rapid propagation through larger RT blocks further expedites the diagnostic information collec- tion process compared to gate-level circuit traversing schemes. The storage and computational benefits delivered by the tracking of information regarding grouped fault effects strongly depend on the fault effect grouping criteria; the mutual manifestation behavior of the faults in a group constitutes the diagnostic information to be tracked. In this work, we analyze the functionality of common RT-level mod- ules so as to identify the fault effect grouping criteria that enable an in- creased propagation ability of the diagnostic information. We provide an analysis that captures and exploits the monotonic information flow inherent in various RT-level operators. Such a regularity helps model the diagnostic information propagation through the corresponding RT modules. Based on this analysis, fault effects are judiciously grouped, enabling the preservation of the group-characterizing information in propagation through RT-level modules. In this paper, we propose an RT-level diagnosis methodology based on the computation of manifestation information regarding grouped fault effects. Not only the execution of the RT-level tool is signifi- cantly faster compared to that of the gate-level techniques, but also considerably smaller storage size is required for the output diagnostic information. The proposed diagnosis tool is able to deliver maximal possible diagnostic resolution; not only are the fault modules identi- fied but furthermore the gate-level faults that account for the defective chip behavior are pinpointed accurately. The diagnosis methodology we propose is customizable to any fault model, promising to deliver further enhanced defect location capabilities. 2. RT-LEVEL APPROACH TO DIAGNOSIS While attaining high diagnostic resolution is crucial in the identi- fication of the cause of IC failures, computational and storage chal- lenges complicate the diagnostic information computation process. An RT-level diagnosis approach is capable of responding to these challenges. Rapid propagation of the fault manifestation informa-