RESEARCH ARTICLE Integrating flipped drain and power gating techniques for efficient FinFET logic circuits Ajay Kumar Dadoria 1 | Kavita Khare 2 | T.K. Gupta 2 | Uday Panwar 2 1 ECE, MANIT Bhopal, India 2 Electronics and Communication, Maulana Azad National Institute of Technology, India Correspondence Ajay Kumar Dadoria, ECE, MANIT Bhopal, India. Email: ajaymanit0@gmail.com Abstract Power dissipation is a main attention for designing complementary metal oxide semiconductor Very Large Scale Integration (VLSI) circuits in deep sub‐micron technology. Constant field device scaling leads to high transistor density, reduction in power supply, lower threshold voltage, and reduction in oxide thickness. This gives rise to short channel effects and increases the leakage currents causing power dissipation. In this paper, based on literature survey, new flipped drain gating (FDG) technique is proposed for mitigation of leakage currents; further FDG technique is integrated with power gating technique which makes power dissipation lower than FDG. Proposed techniques are inte- grated with FinFET technology and applied on Logic Gates and bench mark circuits on HSPICE simulator. Simulation is carried out at 27°C temperature by using 20 to 7‐nm Berkley Predictive Technology Module. Simulation results at 10‐MHz frequency shows maximum saving in leakage power using FDG technique at input vector 01 as 80.35% compared with conventional drain gating for EXOR logic. Similarly, FDG technique saves maximum dynamic power of 25.98% when compared with conventional drain gating for AND logic. KEYWORDS drain gating, FDGT, FinFET, low power, LSTP 1 | INTRODUCTION Technology scaling reduces transistor size but suffers from undesirable short channel effects which results in drain‐ induced barrier lowering. 1,2 Short channel effects are overcome by using multigate field effect transistor (FET) known as FinFETs. Vertical channel structures (gates) which resemble fish fins are used in FinFET. These fins are typically lightly doped or undoped; therefore, the improvement in carrier mobility and reduction in the doping fluctuation in a double gate (DG) are compared with the bulk transistor. The cross‐sectional view of the generic plane DGFET (FinFET) is shown in Figure 1. The overlapped gate fin is shown here. 3 FinFET devices have excellent performance improvement and low power characteristics which results in higher I ON /I OFF ratio and suppress the leakage current and faster the switching speed of the circuit. 4 In the next section, we will talk about some properties of FinFET technology, measurement of I ON and I OFF current with different technology, then study of conventional drain gating technique, and finally study of power gating tech- nique. The proposed circuit and its combinations are discussed in Section 3. In Section 4, results and discussion of existing and proposed work and finally conclusions are presented in Section 5. Received: 1 December 2017 Revised: 31 January 2018 Accepted: 11 March 2018 DOI: 10.1002/jnm.2344 Int J Numer Model. 2018;e2344. https://doi.org/10.1002/jnm.2344 Copyright © 2018 John Wiley & Sons, Ltd. wileyonlinelibrary.com/journal/jnm 1 of 14