This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 1 Lowcomplexity Generic VLSI Architecture Design Methodology for N th Root and N th Power Computations Suresh Mopuri and Amit Acharyya , Member, IEEE Abstract—In this paper, we propose a low complexity archi- tecture design methodology for fixed point root and power com- putations. The state of the art approaches perform the root and power computations based on the natural logarithm-exponential relation using Hyperbolic COordinate Rotation DIgital Computer (CORDIC). In this paper, any root and power computations have been performed using binary logarithm-binary inverse logarithm relation. The designs are modeled using VHDL for fixed point numbers and synthesized under the TSMC40-nm CMOS technology @ 1 GHz frequency. The synthesis results shows that the proposed N th root computation saves 19.38% on chip area and 15.86% power consumption when compared with the state of the art architecture for root computation without compromising the computational accuracy. Similarly, the proposed N th power computation saves 38% on chip area, 35.67% power consumption when compared with the state of the art power computation with out loss in accuracy. The proposed root and power computation designs save 8 clock cycle latency when compared with the state of the art implementations. Index Terms— CORDIC, logarithm, exponential, VLSI archi- tecture, root computation, power computation, hyperbolic CORDIC. I. I NTRODUCTION R OOT and power computations have been used in dif- ferent areas such as atmospheric models, digital image synthesis, 3-D graphics and many VLSI signal processing applications [1]–[3]. However, the design and implementation of low complexity as well as highly accurate VLSI architecture of such N th root and N th power computation is a challenging task for real time resource constrained platform. There are various approaches available for root compu- tation. The well known method is Newton-Raphson (NR) method requiring an initial guess which may result different precision in the outputs [4]–[6]. The hardware complexity of NR method increases with increasing value of N . A General Manuscript received March 2, 2019; revised July 13, 2019; accepted August 29, 2019. This work was supported in part by the Science and Engineering Research Board (SERB), Government of India, for the project entitled “Intelligent IoT enabled Autonomous Structural Health Monitor- ing System for Ships, Aeroplanes, Trains and Automobiles” through the Impacting Research Innovation and Technology (IMPRINT) Program under Grant IMP/2018/000375. This article was recommended by Associate Editor A. Cilardo. (Corresponding author: Amit Acharyya.) The authors are with the Department of Electrical Engineering, Indian Institute of Technology Hyderabad (IIT Hyderabad), Hyderabad 502285, India (e-mail: ee13p0004@iith.ac.in; amit_ acharyya@iith.ac.in). Digital Object Identifier 10.1109/TCSI.2019.2939720 digit-recurrence algorithm is presented in [7] whose hardware complexity like NR approach, also depends on N . In [8], a top-level approach has been presented based on the binary logarithm-binary inverse logarithm relation i.e, R 1 N = 2 log 2 ( R) N . But this approach [8] did not present the implementation details of the binary logarithm, division and binary inverse logarithm. Another approach was presented in [9] based on the natural logarithm-exponential relation i.e, R 1 N = exp( ln( R) N ) where the natural logarithm, division and exponential com- putations are performed using CORDIC. On the other hand, the powers are computed using multipliers [10]–[13], in which the square and cube operations were computed using reduced partial product arrays and ancient Indian Vedic mathematics. However, these approaches [10]–[13] are not generic for the N th power computation. Such a generic approach for N th power computation is proposed in [14] based on the natural logarithm-exponential relation i.e, R N = exp(ln( R) × N ) where the natural logarithm and exponential computations are performed using CORDIC. It is well known that the CORDIC performs several tasks such as trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division and square-root using shift add operations [15]–[21]. However, the conver- gence and precision of the CORDIC depend on its negative index (m) and positive (n) boundaries respectively [15], [21] (elaborated in section II, please see equation (11), (12) and (13a)). The CORDIC convergence boundary (m) poses the following limitations on the state of the art N th root and N th power computations [9], [14]. • The CORDIC negative index boundary (m) limits the input range of R and N . As m value increases the input ranges of R and N will increase. • As m value increases, number of CORDIC iterative stages will increase in turn the hardware complexity, area, power consumption and latency will increase. Addressing the fore mentioned limitations, in this paper, • We propose a low complexity architecture design method- ology for the N th root and N th power computation based on the binary logarithm-exponential relation using CORDIC. • We propose Binary Hyperbolic CORDIC algorithm to perform the binary logarithm and inverse binary logarithm computations. 1549-8328 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. 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