Bahria University Journal of Information & Communication Technology Vol .2, Issue 1, November 2009 High Speed Programmable FIR Filters for FPGA Shahid Hassan 1, 2 , Farhat Abbas Shah 1, 2 , Umar Farooq 1 Abstract ----- This paper presents high speed programmable FIR filters specifically designed for FPGA. Vendor provided components are used in Filter’s MAC unit. FIR filters are programmable in terms of new coefficients. Both UDF & FDF of FIR filters are analyzed. Results are presented for 16bit-20taps and 8bit-20taps on 2s100tq144-6 of Xilinx Spartan-II FPGA. Maximum speed improvement of about 64.83% for 16bit-20taps, 49.70% for 8bit-20taps filter in UDF FIR filters and 48.3% for 16bit- 20taps, 21.47% for 8bit-20taps in FDF FIR filters have been achieved utilizing a small variation of area in some cores. Index Terms ---- Digital Signal Processing (DSP), Multiply Accumulate (MAC), Finite Impulse Response (FIR) filters, Application Specific Integrated circuits(ASIC) , Field Programmable Gate Arrays(FPGA), System-on-Chip (SoC) Design. UDF (Unfolded Direct Form), FDF (Folded Direct Form). I: INTRODUCTION Present era of mobile computing and multimedia technology demands high performance and low power VLSI digital signal processing (DSP) systems. The availability of larger FPGA devices has started a shift of SoC designs towards reprogrammable FPGAs, thereby starting a new era of System-on-a-Reprogrammable-Chip (SoRC). Parameterized IP cores remain a standard way to utilize the improvement in FPGA technology and contend with time to market pressure through reuse. [2] One of the most widely used operations in DSP is finite-impulse (FIR) filtering which performs the weighted summations of input sequences. There are two main types of FIR filter implementations namely sequential and parallel [3]. 1Department of Electrical Engineering, University of Engineering and Technology Taxila, Pakistan 2National Engineering and Scientific Commission, Islamabad, Pakistan shahid_uet38@yahoo.com , fas77pk@hotmail.com , umarfarooq@uettaxila.edu.pk Former is selected for its low complexity and area over head as compared with the later. Sequential implementation requires a single multiplier as compared to multiple adders and multipliers required in parallel implementation. Due to increasing complexity of DSP systems and large computations, filtering operations at times become slow. This makes high speed design an important area of research in the field of digital design. Most of the previous work has been limited to the design of FIR filters with fixed coefficients [6]. FIR filter with programmable coefficients are used in many applications like adaptive pulse shaping and signal equalization on the received data in real time. So filter coefficients have been programmable in the design. In past lots of work has been done for high speed FIR filters but most of them have used user defined components. So decision was made to use the components provided by the vendor itself. Proper configuration of components is required before its use. Idea of this work evolved from the fact that vendor provided components are the most suitable for FPGA implementation. Organization of the paper is as follows: Section-II describes the implementation of reference core, vendor provided components that can be use in FIR filter cores, and their proper implementation. Results of the reference core and the new implemented cores are presented in Section-III. Finally, conclusion and future work has been shown in the end. II: IMPLEMENTATION a) Reference FIR Filter Core Implementation FIR Filtering is one of the most widely used operations in Digital Signal Processing (DSP) devices. The basic equation of the UDF FIR Filter is given as (1) h m ‟s are the filter coefficients and xn-m „s are the filter input sample values and yn is the output.     M m m n x m h n y 0 ) ( ) ( ) ( 45