Design of Resistive Non-Volatile Memories for Rad-Hard Applications Nicola Lupo * , Cristiano Calligaro † , Roberto Gastaldi † , Christian Wenger ‡ , Franco Maloberti * * Department of Electrical, Computer and Biomedical Engineering, Univerity of Pavia, Pavia, Italy † RedCat Devices, Via Moncucco 22, Milan, Italy ‡ IHP-Microelectronics, Frankfurt (Oder), Germany Abstract—In this paper a rad-hard design flow for emerging non-volatile memories is discussed. The always growing demand of memory performances is driving to an increasing investigation in new technologies; many emerging technological solutions have been introduced and, as all of them are still an embryonic stage, it is necessary to improve and optimize their characterization process in order to achieve as soon as possible the reliability necessary to stand out in the market. Among them, the resistive memories have recently raised a significant interest for space and high-energy applications. In this scenario, hence, it may be effective and crucial to design an architecture capable to manage different demands like the use in radiation environment. At this purpose, a radiation-hardened design of a 1Mbit resistive non- volatile RAM providing full bit DMA access is proposed. A basic RRAM cell and its structure are explained and the radiation hardened architecture that includes a redundant differential approach presented. I. I NTRODUCTION In the last years communication technologies have led to a fast and aggressive evolution of the consumer electronics. Personal communications mainly exchange multimedia con- tents and huge amounts of data are constantly transmitted and stored, thus demanding larger and larger non-volatile memories. Moreover, the Internet of Things (IoT), i.e. the use of smart devices in every aspect of life, leads to complex system architectures in which the embedded non-volatile mem- ories play an always-expanding role. More critical are space applications that require robustness against radiation damages and very high reliability. While flash-memories density increases, metrics such as endurance, reliability, and overall performance decline [1]. Therefore, new flash-based structures have been studied in order to obtain larger capacity with sufficient reliability and performances; possible avenues are the 3D approaches, studied for stacked structures and vertical-developed arrays [2]. Beside this, alternative technologies have been developing; among them, the ones based on resistivity change are raising interest because of their cost effectiveness, performance, low-power consumption, and small footprint. In particular, recent advances in the performance of resistive random access memory (RRAM) have engendered significant interest for system-on-chip (SoC) applications in Si-based CMOS technologies for radiation hardened applications. As resistive memories do not store information by mean of charge retention, they show an intrinsic robustness against single event upset (SEU) caused by high-energy particles. This radiation tolerance can be improved by purely focusing on the radiation hardening of the peripheral CMOS circuits [3]. Research is still ongoing because understanding of the inter- cell and intra-cell variability of memory elements in a memory array is relevant for process optimization [4][5]; therefore, an accurate analysis of the real behavior under radiations of the cell array as a memory module is necessary. This paper analyzes radiation-hardening design issues hav- ing a 0.25μm CMOS technology as implementation vehicle. An accordingly designed prototype will permit experimental processes useful to optimize the technology and improve performances for an effective use of resistive memories in rad- hard applications. II. THE RRAM CELL A basic RRAM memory cell implemented with a 1T-1R structure is considered: a nMOS transistor is used as a selector to access a HfO 2 -based resistive element implemented with a Metal-Insulator-Metal (MIM) structure. Given the wide range of possible transition metal oxides, HfO 2 -based RRAM pro- vides an ideal CMOS back-end-of-line (BEOL) compatibility with sufficient performance parameters and, thus, considerable progress has been made in integrating 1T-1R devices as well as in understanding the physical and chemical properties of the resistive switching behavior [6][7]. The basic cell technology steps are the following: first the selecting element, the nMOS transistor, is fabricated. After that, featuring width (W) of 1.14μm and length (L) of 0.24μm, the resistive switching cell of MIM is placed between the metal levels 2 and 3, as illustrated in Fig. 1. In order to study the impact of the bottom electrode deposition process, an additional AVD TiN with thickness of 20nm is deposited on top of the metal 2 stack. In addition, in order to study thickness dependence, HfO 2 films with thickness of 10nm are deposited at 400 ◦ C by using AVD method. Finally, HfO 2 is capped by 7nm ionized metal plasma (IMP) Ti and 20nm PVD TiN. The devices is then induced by a 400 ◦ C/30 min post-metallization annealing (PMA) step. The described fabrication steps are to fabricate an observ- able structure implementing the basic concept of a resistive cell: a device with a conductive filament (CF) in it obtained either by varying the intensity of the current flowing through the device (unipolar approach) or by switching the polarity of the voltage applied (bipolar approach). In the second case a 978-1-4799-5341-7/16/$31.00 ©2016 IEEE 1594