Towards Automatic Thermal Network Extraction in 3D ICs Mingyu Li University of Massachusetts 301 Knowles Engineering Building Amherst, MA, 01003 mingyul@umass.edu Santosh Khasanvis BlueRiSC Inc. 400 Amity Street Amherst, MA, 01002 santosh@bluerisc.com Jiajun Shi University of Massachusetts 301 Knowles Engineering Building Amherst, MA, 01003 jiajun@umass.edu Sachin Bhat University of Massachusetts 201 Knowles Engineering Building Amherst, MA, 01003 sachinbalach@umass.edu Mostafizur Rahman University of Missouri 570A Flarsheim Hall Kansas City, MO, 64110 rahmanmo@umkc.edu Csaba Andras Moritz University of Massachusetts 207 Knowles Engineering Building Amherst, MA, 01003 andras@ecs.umass.edu ABSTRACT Thermal management is one of the critical challenges in 3D integrated circuits. Incorporating thermal optimizations during the circuit design stages requires a convenient automatic method of doing thermal characterization for feedback purposes. In this paper, we present a methodology, which supports thermal characterization by automatically extracting the steady-state thermal modeling resistance network from a post-placement physical design. The method follows a two-level hierarchical approach. It does fine- grained thermal modeling for standard cells, and then at higher level assembles the thermal modeling network of the input physical design by using the built standard cell thermal models, and adding the information on inter-cell connections as well as implemented thermal management features. The methodology has been implemented in Skybridge-3D-CMOS technology, but can be employed in other fine-grained 3D directions such as monolithic 3D CMOS. Large scale benchmarking has been performed, showing the ability of doing automated fine-grained thermal characterization in the order of seconds per thousands of 3D standard cells. In addition, the methodology is employed to highlight implications of added thermal extraction features. CCS Concepts • Hardware ➝ Emerging technologies Keywords 3D heat management; thermal modeling network extraction; Skybridge; Skybridge-3D-CMOS 1. INTRODUCTION 3D integration is an emerging technology to enable surpassing many of the current limitations in traditional CMOS scaling [1]-[4]. However, the thermal problem is a critical challenge in 3D integrated circuits (ICs) due to the higher transistor density and worse heat dissipation compared with conventional planar IC [5]- [6]. Researchers have been working on tackling the thermal issues in 3D IC, and thermal-aware CAD is one of the important directions. It incorporates thermal optimizations during various design stages such as floorplanning, placement and routing [7]-[9]. During the optimization, the tool has to repetitively evaluate the design in the thermal domain for feedback, which necessitates a method to support the automatic thermal characterization of large- scale physical designs. As one of the directions in 3D IC, the Skybridge fabric has been proposed as a vertically-composed fine-grained 3D IC fabric technology, which builds on uniform vertical nanowire templates and utilizes novel assembly, interconnect and heat extraction structures designed with a 3D mindset [10]-[14]. In Skybridge, fine-grained 3D thermal management is supported by incorporating specially-architected intrinsic thermal management fabric components, which allow heat extraction and dissipation from heated regions in the layouts to the substrate, and thus prevent hotspot development. Implementing these thermal features (either manually or with automatic tools) needs automatic thermal characterization. Also, the thermal characterization needs to be able to capture the effects of the intrinsic fabric-level thermal management components in the circuits. Such a circuit-level thermal mitigation mindset, a likely requirement in emerging fine- grained 3D, in conjunction with automated extraction of thermal networks have not been reported yet to the best of our knowledge. In this paper, we focus on a methodology, which supports the automatic thermal characterization by automatically extracting the steady-state thermal modeling resistance network for a physical design in 3D IC. This methodology employs a hierarchical mindset; at the intra-cell level models the standard cell layouts with detailed analogous thermal modeling circuits, and then at higher level assembles the thermal modeling network for the whole physical design by reusing the built standard cell thermal models. It includes the information on cell placement & routing and thermal features into the modeling network. In particular, it captures the effects of detailed inter-cell routing information as well as the implemented thermal management fabric components in the circuit design. This methodology can apply to various flavors of Skybridge fabrics and other 3D directions including TSV-based and monolithic gate-level / transistor-level 3D IC. The rest of this paper is organized as follows. In Section II we provide an overview of Skybridge fabric. In Section III we introduce the intrinsic fabric-level heat management features in Skybridge. In Section IV we introduce the proposed methodology of automatic thermal resistance network extraction focusing on the S3DC use case. In Section V we show thermal characterization Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Permissions@acm.org. Nanoarch’16, July 18–20, 2016, Beijing, China © 2016 ACM. ISBN 978-1-4503-4330-5/16/07…$15.00 DOI: http://dx.doi.org/10.1145/2950067.2950095