Multiply-by-two gain stage with reduced mismatch sensitivity H. Zare-Hoseini, O. Shoaei and I. Kale A new multiply-by-two gain stage is presented suppressing the gain sensitivity to capacitor mismatches. Using one operational amplifier in three phases, a gain of two, which is not highly influenced by the mismatches between the capacitors, is achieved. Circuit- level Monte-Carlo simulations support the reduction of matching requirements. Introduction: The basic core of a standard pipeline ADC, used as a fast, high resolution and moderate power consumption converter, relies on an MBT (2) function. This multiply-by-two gain stage (MBT-GS) needs an accuracy and linearity performance as good as the whole converter precision [1]. In the conventional MBT-GS, shown in Fig. 1a, the accuracy of the gain (2) is strongly related to the mismatches between the capacitors. Such a matching requirement, especially when other nonidealities and nonlinearities are taken into account, is the biggest problem and the bottleneck for achieving higher resolution in such converters. Fig. 1 Schematic of proposed MLS MBT-GS The capacitor error-averaging technique using two opamps in three phases [1], the same technique using a single opamp but in four phases [2] and another technique using two opamps operating in four phases [3] have been proposed to solve the mismatch sensitivity in the analogue domain. In this Letter, a new MBT-GS is presented, which suppresses the dependency of gain on the capacitors’ mismatches using one opamp in three phases. Conventional MBT-GS: In the conventional GS shown in Fig. 1a, in the sampling phase (f 1 ), the input signal is sampled by the two nominal identical capacitors, and in the holding phase (f 2 ), one of them is replaced by the feedback and the MBT (2) function is produced. If the capacitors are assumed to be slightly mismatched from their ideal value, i.e. (C i ¼ C(1 þ d i )) where d i is the Gaussian random variables of relative mismatch error with mean ¼ zero and a variance of s c 2 , the gain will be: g ¼ V o =V in ffi 2 þðd 1  d 2 Þ=2 ð1Þ Assuming mismatches are uncorrelated, we have E[g] ¼ 2 and Var rel [g] ¼ s c 2 =2 (for the fully differential version, Var rel [g] ¼ s c 2 =4) where E[  ] and Var rel [  ] denote the mean and the relative variance. So, the mismatches affect the gain precision directly. Mismatch-less-sensitive MBT-GS: To attenuate the dependency of gain on the capacitors’ mismatches, the mismatch-less-sensitive scheme shown in Fig. 1c is proposed. The key point in the proposed topology is that the amount of the transferred charge is only depen- dent on one of the capacitors, here C1, instead of the two capacitors, C1 and C2 in the conventional structure. The clock scheme is shown in Fig. 1b. During f 1 , as shown in Fig. 1d, the input signal is sampled by C 1 and simultaneously an equal amount of charge on C 1 is transferred into the feedback capacitor, C 2 . During f 2 , the two capacitors are replaced by each other and, consequently, the charge of C 2 is transferred to the feedback capacitor, i.e. C 1 . Therefore V 0 ¼ Q c 1 ðf 2 Þ=C 1 ¼ðQ c 1 ðf 1 Þ Q c 2 ðf 1 ÞÞ=C 1 ¼ 2V in ð2Þ Equation (2) shows that the output voltage does not suffer from the mismatches between the capacitors. In the resetting phase (f 3 ), the capacitors reset so that they are ready for the next sampling phase. Although in the ideal case it seems that the mismatch problem is completely removed, there are some nonidealities affecting the preci- sion. The main problem of the technique arises from the parasitic capacitor at node a as shown in Figs. 1c and d, which is the summation of the parasitic plate capacitance of C 2 and the three parasitic ones of the connected switches and is denoted by C p . During f 1 , C p is charged by the output voltage of around V in . During f 2 , this undesirable charge is completely induced to the inverting input node of the opamp and so goes to the feedback. So, the output voltage will be: V 0 ¼ 2ð1 þ C p =C 1 ÞV in ð3Þ To eliminate the error from this parasitic capacitance, a fully differential structure is used and an amount of charge equal to the one induced parasitically by C p to the inverting input node of the opamp is induced into the non-inverting input node, and vice versa. With this, the parasitic charge will appear as a common-mode input and disappear in the differential mode output by common-mode rejection ratio. This func- tion is well designed and incorporated into the fully differential version of the technique, as shown in Fig. 2. As seen in this Figure, the complementary of each feedback circuit in the sampling phase is added to the GS. During f 2 , each complementary circuit is connected to an input node of the opamp, and its pair is connected to the other one. For example, in f 2 , while the C 2 circuit is connected to the inverting input node of the opamp, the complementary of it, which is the C 6 circuit, is connected to the non-inverting one. Fig. 2 Modified mismatch-less-sensitive GS scheme To have the complementary circuits exactly the same as their counterparts (in order to have better matching and to reduce the charge injections in the switches), all the main circuit switches are incorporated into the complementary ones, even though some are always off. Assuming the modelled parasitic capacitors with the Gaussian random variables of relative mismatch error of d pi with mean ¼ zero and a variance of s p 2 , the gain of the circuit will be: g ¼ V 0 =V in ¼ 2 þðC p =2CÞðd p 2 þ d p 4  d p 5  d p 6 Þ ð4Þ If the component mismatches are uncorrelated, we have E[g] ¼ 2 and Var rel [g] ¼ (C p =C) 2  s p 2 =4. Considering the same relative variances for all the components, it is clear that the new architecture decreases the ELECTRONICS LETTERS 17th March 2005 Vol. 41 No. 6