THREE-DIMENSIONAL DIGITAL FILTERING ALGORITHM
FOR PARALLEL DSP IMPLEMENTATION
M. Aziz, S. Boussakta and D. C. McLernon
The Institute of Integrated Information Systems
School of Electronic and Electrical Engineering
University of Leeds, LS2 9JT
Leeds, UK
Email: (m.aziz, s.boussakta, d.c.mclernon)@ee.leeds.ac.uk
ABSTRACT
In this paper we present a 3-D parallel filtering
algorithm. This algorithm is highly parallel and
efficient as it eliminates the overhead associated
with the overlapping segments in the block-
filtering approach. It also lifts the restrictions on
the input size for high efficiency in the block-
filtering algorithm, as both the 3-D input data
and impulse response of the system are
decimated into eight subsections each. These
subsections can be simultaneously and
independently processed. The results of the
implementation of the 3-D parallel filtering
algorithm on multi-DSP platform is presented
and discussed showing a high performance
reflected by the highly parallel architecture and
good memory distribution of the 3-D parallel
algorithm.
1. INTRODUCTION
The utilisation of multiple DSP systems for
parallel processing of computationally
demanding applications is growing fast [1-5].
The field of 3-D filtering and multidimensional
signal processing is a good candidate for parallel
processing due to the large amount of
computations required. In fact the growing
importance of parallel processing is reflected by
the large number of applications that embrace it
such as, image filtering [1], medical imaging [2],
machine vision [3], and many more.
The areas of linear and non-linear 3-D digital
filters have received increasing attention in
recent years. 3-D filters inherently belong to the
class of digital systems, since they are difficult to
implement by analog circuits. Consequently
these filters have attracted the interest of
researches in the area of digital signal
processing. In order to implement 3-D and
multidimensional filters extensive computations
are required, and thus their application to date
has been limited. The many advances and
developments in VLSI and parallel computation
has over come this problem [6-8], as more
components and advanced parallel techniques,
i.e. SIMD, VLIW and pipelining, are being
utilised and assembled in low cost systems [6].
In this paper a 3-D parallel digital filtering
algorithm is presented. The development and
mathematical analysis of the algorithm is given
and the run time results for the implementation
of the 3-D parallel digital filtering algorithm on a
multi-DSP card [9] are presented and discussed.
2. 3-D PARALLEL ALGORITHM
DEVELOPMENT AND ANALYSIS
The 3-D parallel filtering algorithm is shown in
Figure 1. This algorithm is divided into three
main stages. The first stage is the 3-D input
decimation algorithm. The second stage is the 3-
D filtering of the different segments of the input
and impulse response. And the third stage is the
output interpolation and reconstruction.
2.1. 3-D Input Decimation Algorithm
The 3-D digital filtering of two 3-D inputs
1 2 3
( , , ) x n n n
1 2 3
( , , ) hn n n
of size and
of size (
( ) N N N × ×
) M M M × × , is carried
out by direct convolution given by the equation:
( )
( )
1 2 3
1 1 1
1 2 3 1 2 3
0 0 0
1 1 2 2 3 3
( , , ) , ,
, ,
N N N
m m m
yn n n xm m m
hn m n m n m
− − −
= = =
=
− − −
∑∑∑
(1)
where the final output dimensions are
1 2 3
0 , , n n n N M 1 ≤ ≤ + − . However, the 3-D
parallel algorithm decimates each input into 8-
segments of equal sizes. The decimation by 2
process for the input data block
1 2 3
( , , ) x n n n is
defined as:
( ) (
)
123
1 2 3 1 1
2 2 3 3
, , 2 ,
2 ,2
iii
x n n n x n i
n i n i
= +
+ +
(2)
where takes the binary values (0 or 1),
i.e. 000, …, 111. So that the eight segments of
input
1 2 3
, , ii i
1 2
( ,
3
, ) x n n n are:
0-7803-7750-8/03/$17.00 ©2003 IEEE. ICIP 2003