Automated synthesis of asynchronous event-based interfaces for neuromorphic systems Hesham Mostafa, Federico Corradi, Marc Osswald, and Giacomo Indiveri Institute of Neuroinformatics, University of Z¨ urich and ETH Z¨ urich, Z¨ urich, Switzerland Email: {hesham,federico,marc,giacomo}@ini.uzh.ch Abstract—We present an automated design approach that leverages the commonly available digital design tools in order to rapidly synthesize asynchronous event-based interface circuits from behavioral VHDL code. As part of the proposed design approach, we describe a verification methodology that is able to reveal early in the design process potential timing failures in the generated circuits. Due to the fast design cycle, the approach presented allows designers to quickly explore different architectures for asynchronous circuits and compare them using quantitative metrics based for example on power consumption or silicon area. We validated the proposed design method by synthesizing asynchronous interface circuits for a neuromorphic multi-neuron architecture, and fabricating the VLSI device. We present data from silicon that demonstrates the correct operation of the automatically generated circuits. I. I NTRODUCTION Neuromorphic event-based systems generally consist of multiple custom hybrid analog/digital Very Large Scale Inte- gration (VLSI) modules that communicate among each other using the Address Event Representation (AER) [1]. In this representation each source or sender node (e.g., a silicon neuron) is assigned an address, and when it produces an event (e.g., a spike) its address is instantaneously put on a digital bus, using asynchronous logic. Destination nodes (e.g., synapses) can decode and “consume” these asynchronous address-events at the time in which they receive them. In the case of single-sender/single-receiver communication, a handshaking mechanism ensures that all events generated at the sender side arrive at the receiver. Typically signals are encoded using a Bundled Data (BD) representation, in which the address of the sending element is conveyed as a parallel word of sufficient length, and two additional lines are required for the handshaking control signals. Systems containing more than two AER modules are constructed by implementing additional purpose arbitration schemes [2]–[4]. In AER systems therefore time represents itself, input and output address-events are transmitted using asynchronous digital pulses that encode the address of the sending node, and analog information is carried in the temporal structure of the inter-pulse intervals and in their mean frequency. If multiple senders generate events simultaneously, an arbitration scheme makes sure that the addresses do not collide, but are transmitted on the bus in sequence, as shown in Fig. 1. The arbiters that manage event- collisions are implemented using asynchronous digital logic circuits. These asynchronous digital circuits change the state 3 12 2 1 123 1 2 3 REQ ACK REQ ACK REQ ACK 1 2 3 REQ ACK REQ ACK REQ ACK Digital Bus Encoder Decoder Arbitration Neurons (source) Synapses (destination) Fig. 1: AER communication scheme. Neurons send spikes by requesting access (REQ signals) to the arbiter circuit. When the arbiter grants access (ACK signal) the corresponding neurons address is written on a digital bus. A decoder on the receiver side creates a spike for every address on the bus and routes to addressed synapses. The arbiter handles colliding requests (shaded pulses) by sequentially en-queuing them. of their memory elements in response to transitions on the data lines. This is very different from what happens in synchronous logic, where all state transitions occur at the edges of a global clock. Synchronous logic is more common than asynchronous one by far. Indeed the predominance of synchronous logic has led to powerful Electronic Design Automation (EDA) tools that greatly accelerate the design process. While there have been recent advances in the research and design of asynchronous logic, especially for neuromorphic systems [5]– [7], there is still no mature and readily available digital design flow for the development and automated design of asynchronous circuits. As a consequence, most asynchronous digital circuits designed by the neuromorphic engineering community are done manually, following a time consuming and error-prone process. In this paper we propose a new method for adapting widely available synchronous digital design tool sets to automatically synthesize asynchronous AER arbitration and interfacing circuits, and present experimental results from a fabricated prototype chip. We describe this design flow methodology in Section II, and its application to the design of AER interface circuits in Section III. We present measurements from silicon in Section IV. Section V presents a discussion of the results and conclusions. II. AUTOMATIC SYNTHESIS OF BASIC ASYNCHRONOUS CIRCUITS The automated design flow is shown schematically in Fig. 2. It is based on the design flow for synchronous digital circuits.