Binary mask side lobe suppression using space scattering bar Sungsoo Suh a, * , Sukjoo Lee a , Kyoung-yoon Back b , Sungwoo Lee a , Youngchang Kim a , Sangwook Kim a , Hanku Cho a a Samsung Electronics, Co. Ltd., Memory Division, Process Development Team, San #16 Banwol-Dong, Hwasung-City 445-701, Republic of Korea b Samsung Electronics, Co. Ltd., Memory Division, NRD-P/J, San #16 Banwol-Dong, Hwasung-City 445-701, Republic of Korea Available online 27 January 2007 Abstract Use of off-axis illumination such as dipole and cross-pole to obtain minimum dense pitch resolution limits process margin due to side lobe defect pattern formation. Side lobe or ghost images are unwanted additional patterns formed at wafer image at certain pitch range where intensity drop occurs [I. Hur, Proc. SPIE 2440 (1995) 278], and there are limited ways in which ghost images can be reduced. One way to suppress ghost image is to use multi-pole illumination and such an illumination condition is difficult to generate using diffractive optic ele- ments so a hard aperture must be used but its use limits throughput. An alternative way is to vary the mask phase in order to somewhat increase the intensity to alleviate the formation at certain pitch range [H. Iwasaki et al., Proc. SPIE 3236 (1997) 544]. But for patterning mem- ory devices at and below 50 nm half-pitch, it is shown that binary mask provides beneficial results over attenuated phase shift mask due so called ‘‘mask induced polarization effect’’ [A. Estroff et al., Proc. SPIE 5754 (2005) 555; W.H. Cheng et al., Proc. SPIE 5992 (2005) 1; S. Teu- ber et al., Proc. SPIE 5754 (2005) 543; Y. Aksenov et al., Proc. SPIE 5754 (2005) 576; I. Ho ¨ llein et al., Proc. SPIE 5853 (2005) 194]. Never- theless, optical proximity corrections are to be performed and maximum obtainable process margin need to be obtained. Hence, a method of optimizing space scattering assist feature positioning and sizing is discussed in this paper. A simplified analysis method to optimize space scattering assist feature insertion is formulated for an optical proximity correction. A simplified model formulation is defined a priori, and its result is compared to results obtained from an empirically calibrated model and indicated a good correlation. Ó 2007 Elsevier B.V. All rights reserved. Keywords: Lithography; OPC; Side lobe; Ghost image; Assist feature 1. Introduction Sub resolution assist features (SRAFs) are typically used to increase across pitch performance and process margin of semi-dense to isolated bars for a clear-field mask while space scattering assist features are utilized for a dark-field mask to give an appearance of dense fea- tures. Contained within a flash memory device gate-poly layer, a repeating set of pattern of differing pitches exist. Use of an off-axis illumination such as dipole and cross- pole to obtain minimum dense pitch resolution limits pro- cess margin due to side lobe defect pattern formation (Fig. 1). Side lobe or ghost images are unwanted addi- tional patterns formed at wafer image at certain pitch range where intensity drop occurs [1], and there are lim- ited ways in which ghost images can be reduced. One way to suppress ghost image is to use multi-pole illumina- tion and such illumination is difficult to generate using diffractive optic element and hard apertures must be used but its use limits throughput (Fig. 2). An alternative way is to vary the mask phase in order to somewhat increase the intensity to alleviate the formation at certain pitch range [2]. But for patterning memory devices at and below 50 nm half-pitch, it is shown that binary mask provides beneficial results over attenuated phase shift mask due so called ‘‘mask induced polarization effect’’ [3–7]. For a binary mask type, space scattering assist features may be inserted to alleviate the unwanted imaging within the process window provided that the critical dimension is 0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.01.039 * Corresponding author. Tel.: +82 31 208 2786; fax: +82 31 208 3019. E-mail address: sungsoo.suh@samsung.com (S. Suh). www.elsevier.com/locate/mee Microelectronic Engineering 84 (2007) 755–760