Ultra Low Power Full Adder Topologies Farshad Moradi 1 , Dag.T. Wisland 1 , Hamid Mahmoodi 2 ,Snorre Aunet 1 ,Tuan Vu Cao 1 , Ali Peiravi 3 1 Nanoelectronics Group, Department of Informatics, University of Oslo, NO-0316 Oslo, NORWAY 2 School of Engineering San Francisco State University, 1600 Holloway Avenue, San Francisco, CA 94132, USA 3 School of Engineering, Ferdowsi University of Mashhad, Mashhad, IRAN Emails: 1 {moradi, dagwis,sa,caovu}@ifi.uio.no, 2 mahmoodi@sfsu.edu, 3 peiravi@ ferdowsi.um.ac.ir Abstract: In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (Gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65nm standard models are used for simulations. Keywords: GDI, SERF, Full adder, Subthreshold I. INTRODUCTION With the rapid development of portable digital applications, the demand for increasing speed, compact implementation, and low power dissipation triggers numerous research efforts [1]-[4]. The role of power dissipation in VLSI systems is pervasive. For high performance design, power dissipation can be the limiting factor to clock speed and circuit density because of the inability to get power to circuits or to remove the heat that they generate. For portable information systems, power dissipation has a direct bearing on size, weight, cost, and battery life. Consequently, power dissipation is becoming widely recognized as a top-priority issue for VLSI circuit design. The challenge facing the VLSI designer is to find and effectively apply circuit techniques that can balance the needs for performance with those of power dissipation [5]. Therefore ultra low power circuits design becomes the major candidates for portable applications. One common technique for reducing power is power supply scaling. For CMOS circuits the cost of lower supply voltage is lower performance. Scaling the threshold voltage can limit this performance loss somewhat but results in increased leakages [6]. Other techniques used in low power design include clock gating and dynamic voltage/frequency scaling [7], [8]. Subthreshold circuit design involves scaling the supply voltage below the threshold voltage, where load capacitances are charged/discharged by subthreshold leakage currents. Leakage currents are orders of magnitude lower than drain currents in the strong inversion regime, so there is a significant limit on the maximum performance of subthreshold circuits. Therefore, traditionally, subthreshold circuits have been used for applications which require ultra-low power dissipation, with low-to-moderate circuit performance [9]. The 1-Bit Full adder design is one of the most critical components of a processor that determines its throughput, as it is used in ALU, the floating point unit, and address generation in case of cache or memory accesses [9]. A variety of full adders have been reported in [10]-[13]. One of the most well known full adders is the standard CMOS full adder that uses 28 transistors as shown in Fig.1. In [10] the sense energy recovery full adder (SERF) is presented. The topology of this circuit is shown in Fig.2 which requires only 10 transistors to implement a full adder. In [12] different full adder topologies with a low number of transistors are presented. In the next section the drawbacks of these SERF based circuits are described. In this paper different topologies for full adder based on GDI technique are presented. Moreover, several circuit topologies based on SERF full adder are presented for ultra low supply voltage applications. The multi threshold technique is used to improve the operation of the SERF full adder design. II. PREVIOUS WORKS: SERF design uses only 10 transistors to implement a full adder. This circuit operates well at higher supply voltages, but if the supply voltage is scaled to voltages lower than 0.3V, this circuit fails to work. Table.1 describes the behavior of this circuit for different inputs. The rest of the paper is organized as follows: In section II, we briefly describe the previous works on full adder design. Section III presents Fig.1. CMOS standard 28T full adder Table.1 Truth table of SERF full adder design new full adders and some simulations. In Section IV, the simulation results are presented and discussed. Section V is the conclusion. Table 1 shows the SERF operation with different input signals. As it can be seen, the SERF adder (Fig.2 (a)) is confronted with serious problems especially at lower supply voltages. Assume that one of the two input vectors ABCin=”110” and “111” are applied. As seen from Fig.2(a), when A=1 and B=1, the F node voltage is Vdd-Vth. Now if Cin=0 then Cout will be equal to Vdd-2Vth and the Sum signal is going to zero driven by a MOS transistor with its gate connected to Vdd-Vth. When Cin=1, Cout is connected to VDD (may be lower) and the SUM signal will go to Vdd-Vth. Another problem with this design is when the floating node is connected to 0 (A=0, B=1 or A=1, B=0).When Cin is “1”, Cout is charged to Vdd, but when Cin=0, Cout must be discharged to ground using a PMOS pass transistor that cannot fully discharge the output. In this case, Cout is discharged to Vtp which is higher than Vtn. This problem is intensified if the circuit works at subthreshold voltage. If A is at logic “1” , some current leaks to the Cout node which makes COUT to increase even more than Vtp in some cases depending on the sizing of the pass transistors. In this case the Sum value is dependent on the Cin state, for instance, if Cin is “1”, the Sum output is going to Vdd-Vth which is a problem in subthreshold region. The most important problem with SERF full adder is in the case when A=1, B=1 and Cin=0. In this case as mentioned before the output signal reaches VDD. Simulation results show that at VDD=0.3V, the output signal is rising only to 0.1V which is not high enough to change the state of the next stage. To eliminate these problems a new topology must be introduced. This limitation also causes a constraint for lowering the supply voltage. For instance, to have a correct output for SUM it seems that the supply voltage cannot be lowered more than VDD/2+2Vtn indicating that the supply voltage must be higher than VDD/2+0.28v in a 65nm CMOS technology. However this limit depends on the circuit design topology and also the sizing and the device types that are employed. To mitigate this problem, the gates of PT for Cout signal must be connected to VDD during the challenging state (A=B=1, Cin=0). Then the supply voltage may be reduced to as low as Vdd/2+Vth which is estimated to be Vdd/2+0.14. For example when VDD=0.3, in worst case Cout will then be Vdd- Vth=0.16V, which can be used as a high logic. In addition the NMOS pass transistor may be upsized to further lower the supply voltage. It seems to be possible to lower supply voltage to 0.25V. In A=1, B=1, and Cin=0, the equivalent circuit for SUM signal is shown in Fig.3. As it can be seen, we cannot decide exactly the state 978-1-4244-3828-0/09/$25.00 ©2009 IEEE 3158 Authorized licensed use limited to: San Francisco State Univ. Downloaded on December 18, 2009 at 19:32 from IEEE Xplore. Restrictions apply.