Large Random Telegraph Noise in Sub-Threshold Operation of Nano-Scale nMOSFETs J.P. Campbell 1 , L.C. Yu 1,2 , K.P. Cheung 1* , J. Qin 1,3 , J.S. Suehle 1 , A. Oates 4 , K. Sheng 2 1 Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, MD 20899 *kpckpc@ieee.org 2 Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ 08854 3 Departmemt of Mechanical Engineering, University of Maryland, College Park, MD 20740 4 TSMC Ltd., Hsin-Chu, Taiwan 300-77, R.O.C. Abstract--We utilize low-frequency noise measurements to examine the sub-threshold voltage (sub-V TH ) operation of highly scaled devices. We find that the sub-V TH low-frequency noise is dominated by random telegraph noise (RTN). The RTN is exacerbated both by channel dimension scaling and reducing the gate overdrive into the sub-V TH regime. These large RTN fluctuations greatly impact circuit variability and represent a troubling obstacle that must be solved if sub-V TH operation is to become a viable solution for low-power applications. Keywords—RTN, Sub-V TH operation I. INTRODUCTION Traditional device scaling focuses on a balance between performance and power consumption. However, the emergence of power-sensitive products (cell phones, pacemakers, implantable devices) has led to the exploration of circuits which operate in the sub-threshold voltage (sub-V TH ) regime [1]. The sub-V TH paradigm sacrifices a small amount of performance for a comparatively huge power reduction (~V G 2 ) while maintaining the benefits of scaling [2] . Quite recently, this sub-V TH approach has been experimentally realized in prototype microprocessors and SRAM arrays [3, 4]. However, the benefits of sub-V TH scaling do not come without penalty. Since sub-V TH operation reduces device drive current, circuits become significantly less tolerant of noise [2]. While several recent reports detail clever approaches to combat this noise intolerance [2, 3, 5], they do not account for the possibility of large noise increases as device dimensions continue to scale. Specifically, in nano-scaled devices a particularly troubling noise phenomenon called random telegraph noise (RTN) [6] has the potential to severely limit sub-V TH circuit design. RTN is a digital fluctuation in device drain current (I D ) which has already been identified as a large obstacle in super-V TH operation of both SRAM and FLASH memory technologies [7-9]. However, the impact of RTN on sub-V TH operation is only sporadically debated in the literature with very little consensus. Some researchers report a ΔI D /I D inverse channel length dependence (1/L) [10] while others report a more pessimistic 1/L 2 dependence [11, 12]. Some researchers report no dependence on channel width (W) [11] while others report a 1/√W dependence [13]. However, most of these reports focus on larger channel area devices with particular emphasis on the super-V TH regime. Asenov et al. was the first to report simulations of highly-scaled devices [13, 14]. These simulations predict an enhanced ΔI D /I D RTN in the sub-V TH regime. If this enhancement were to be experimentally observed, the implication to sub-V TH circuits would be serious. Surprisingly, there is almost no Frequency [Hz] PSD 2 f 1 Digital Storage O-scope nFET I-V Pre-Amplifier Digital Storage O-scope nFET I-V Pre-Amplifier Frequency [Hz] PSD 2 f 1 Digital Storage O-scope nFET I-V Pre-Amplifier Digital Storage O-scope nFET I-V Pre-Amplifier Figure 1. Schematic illustration of the power spectral density (PSD) of an RTN fluctuation (Lorentzian line shape with slope 1/f 2 ). The schematic representation of our experimental approach is shown in the inset. experimental evidence to examine the validity of this prediction. In this paper we present low-frequency noise characteristics of highly-scaled nMOSFETs as a function of gate overdrive (V G -V TH ) for a variety of channel lengths and widths. As expected, reduction of the channel dimensions reveals a noise mechanism dominated by RTN. This RTN is largest in the sub-V TH regime and reduces as the gate-overdrive is increased to super-V TH values. We also note the presence of occasional giant ΔI D /I D RTN in a small number of the most highly scaled devices. Our collective observations represent a grim outlook for the viability of sub-V TH circuit scaling and identify RTN as a topic which merits further attention. II. EXPERIMENTAL METHODS Our experiments utilize silicon oxynitride (SiON) n- channel MOSFET devices with a physical dielectric thickness of 1.4 nm. The nominal channel widths ranged from 0.085 μm to 1 μm and the nominal channel lengths ranged from 0.055 μm to 1 μm. The RTN measurement apparatus is schematically illustrated in the inset of fig. 1. Source and gate electrodes are biased using battery-powered variable voltage sources, while the substrate electrode is grounded for all measurements. The drain current is monitored by a low-noise 978-1-4244-2934-9/09/$25.00 ©2009 IEEE Authorized licensed use limited to: NIST Virtual Library (NVL). Downloaded on July 27,2010 at 17:09:43 UTC from IEEE Xplore. Restrictions apply.