Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler Infineon Technologies AG Balanstrasse 73 81541 Munich, Germany Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski Mentor Graphics Corporation 8005 S.W. Boeckman Road Wilsonville, OR 97070, USA Abstract This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quality. The System-on- Chip (SoC) design flow and the changes necessary to successfully implement EDT are presented. Experimental results for three SoC designs targeted for automotive, wireless, and data communication applications are provided. These results demonstrate that EDT, with no performance impact, little area overhead, and minimal impact to the flow, results in a significant reduction of scan test data volume and scan test time while maintaining the test quality levels. 1 Introduction Manufacturing test based on scan and automatic test pattern generation (ATPG) has been successfully utilized to test complex SoCs as well as products incorporating a significant amount of embedded logic. Among the factors that contribute to the success of scan and ATPG is that they lend themselves well to automation and provide consistent, reliable, and high quality results. Furthermore, deterministic ATPG techniques provide support for a variety of fault models necessary to achieve high quality test, such as stuck-at, transition, path delay, IDDq, and bridging. Remarkable results illustrating the effectiveness of scan/ATPG methodology are reported in several recent publications [1,2]. While the scan/ATPG technique provides multiple benefits, the cost of this test methodology is continually increasing. This is due to the exponential increase in the scan test data volume, caused by the exponential increase in the complexity of the designs enabled by the ever-reducing feature sizes. In addition, the already high gate-to-pin ratio further increases as a result of the increasing design complexity while the pin count does not increase at the same rate. These factors cause a significant bandwidth problem for the well-established scan test methodology and cause an exponential increase in the test application time [3,4]. The scan test time for SoCs, which today constitutes about 10%-20% of the overall test time, is expected to increase significantly, and dominate the overall test time in the near future. Figure 1 shows that the overall manufacturing test time for a 300k gate design is nearly independent of the number of internal scan chains because scan test time constitutes a small fraction of total test time. However, as designs become more complex with a limited number of external scan pins, scan test time starts dominating, assuming traditional scan/ATPG techniques [4]. Increasing the scan frequency to reduce the test time is not a viable option due to rigid power and area constraints. The recently-proposed low cost ATE approach can help to reduce test-cost-per-second, but does not help in reducing the ever-increasing scan test time and hence only solves part of the problem. In order to increase the throughput of the manufacturing test floor, it is necessary to increase the number of units of installed test equipment, which includes wafer probers and handlers in addition to the low cost ATE. The cost of owning and maintaining this peripheral equipment can easily exceed that of the low cost ATE. Hence to reduce the overall cost of test, it is Relative Test Time at Fixed Scan Frequency 0 2 4 6 8 10 12 14 16 0,00E+00 1,00E+06 2,00E+06 3,00E+06 4,00E+06 5,00E+06 Gate count Normalized test time 10 scan chains 20 scan chains 30 scan chains Figure 1: Gate count vs. overall test time ITC INTERNATIONAL TEST CONFERENCE Paper 47.1 1211 0-7803-8106-8/03 $17.00 Copyright 2003 IEEE