Received June 25, 2021, accepted August 4, 2021, date of publication August 18, 2021, date of current version August 27, 2021. Digital Object Identifier 10.1109/ACCESS.2021.3106171 A Systematic Review of Deep Learning for Silicon Wafer Defect Recognition UZMA BATOOL 1,2 , MOHD IBRAHIM SHAPIAI 1 , (Member, IEEE), MUHAMMAD TAHIR 3 , ZOOL HILMI ISMAIL 1 , (Senior Member, IEEE), NOOR JANNAH ZAKARIA 1 , AND AHMED ELFAKHARANY 1 1 Centre for Artificial Intelligence and Robotics iKohza, Malaysia-Japan International Institute of Technology, Universiti Teknologi Malaysia, Kuala Lumpur 54100, Malaysia 2 Department of Computer Science, University of Wah, Wah 47040, Pakistan 3 Department of Chemical Engineering, School of Chemical and Energy Engineering, Faculty of Engineering, Universiti Teknologi Malaysia (UTM), Skudai, Johor 81310, Malaysia Corresponding author: Mohd Ibrahim Shapiai (md_ibrahim83@utm.my) This work was supported in part by the Ministry of Higher Education of Malaysia through Malaysia Laboratories for Academia–Business Collaboration (MyLAB) under Grant JPT.S(BKPI)2000/016/018/07 Jld.26 (8), and in part by the Universiti Teknologi Malaysia under Grant Q.K130000.2543.21H17 for the project ‘‘Imbalanced strategy for wafer defect classification using fully convolutional neural network. ABSTRACT Advancements in technology have made deep learning a hot research area, and we see its applications in various fields. Its widespread use in silicon wafer defect recognition is replacing traditional machine learning and image processing methods of defect monitoring. This article presents a review of the deep learning methods employed for wafer map defect recognition. A systematic literature review (SLR) has been conducted to determine how the semiconductor industry is leveraged by deep learning research advancements for wafer defects recognition and analysis. Forty-four articles from well-known databases have been selected for this review. The articles’ detailed study identified the prominent deep learning algorithms and network architectures for wafer map defect classification, clustering, feature extraction, and data synthesis. The identified learning algorithms are grouped as supervised learning, unsupervised learning, and hybrid learning. The network architectures include different forms of Convolutional Neural Network (CNN), Generative Adversarial Network (GAN), and Auto-encoder (AE). Various issues of multi-class and multi-label defects have been addressed, solving data unavailability, class imbalance, instance labeling, and unknown defects. For future directions, it is recommended to invest more efforts in the accuracy of the data generation procedures and the defect pattern recognition frameworks for defect monitoring in real industrial environments. INDEX TERMS Wafer map defects, wafer bin map, defect recognition, deep learning, systematic literature review. I. INTRODUCTION Silicon chips are the backbone of the current digital era. The advancements in the emerging technologies of Internet of Things (IoT), Fifth Generation (5G) telecommunication networks, Artificial Intelligence (AI), and the automotive industry have propelled their consumption [1], [2]. Keeping up with the growing demand for semiconductor devices by embracing the efficient, most suitable manufacturing automa- tion practices is more critical in present times. Like other The associate editor coordinating the review of this manuscript and approving it for publication was Zahid Akhtar . manufacturing industries, semiconductor fabrication com- panies aim for maximum productivity by taking measures against yield limiting factors. Among several influencing parameters, wafer fabrication defects are significant [3]. Con- trolling the ratio of defective Integrated Circuits (ICs) deter- mines an IC foundry or wafer fabrication facility (fab)’s productivity and indicates its control on the manufacturing processes [4]. The defects caused by the frontend operations in circuit fabrication reflect the manufacturing equipment and processes’ flaws. They are characterized as random and systematic defects based on their originating factors [5]. Most wafers carry a mix of both types. Fig. 1 shows examples 116572 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ VOLUME 9, 2021