A Novel High-Speed Binary and Gray Incrementer/Decrementer for an Address Generation Unit Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi Krishna M, Sreekanth Reddy P, M.B.Srinivas Centre for VLSI and Embedded System Technologies International Institute of Information Technology-Hyderabad Gachibowli, Hyderabad, 500032, India. Email: srihari@research.iiit.ac.in, {avinashl, kirthikrishna,sreekanthp}@students.iiit.ac.in, srinivas@iiit.ac.in. Abstract An Incrementer/Decrementer (INC/DEC) is a common building block in many digital systems like address generation unit which are used in microcontrollers and microprocessors. In this paper, novel architectures and designs for binary and gray INC/DECs are presented which are more efficient in terms of speed without compromising in power. The proposed architectures lay emphasis on the usage of hybrid logic that is, coupling of transmission gate with CMOS gates at appropriate stages for efficient design. Also, efficient utilization of the output and its complement, available in all existing implementations of gates, is done by using multiplexers in the proposed gray INC/DEC. For a 32-bit input, the proposed binary and gray INC/DEC achieve an improvement of 47%, 33% in delay and reduction of 38%, 28% in power-delay product respectively. 1. Introduction The incrementer/decrementer (INC/DEC) is a digital module which can count up or down by one step and is a common building block in many digital systems like microprocessor, microcontroller and frequency divider [1,2]. It is also mainly used in a address generation unit where optimization of the circuit in terms of power is a important criterion. The current architectures of binary INC/DEC are mainly adder/subtractor-based, counter-based or carry look- ahead adder-based [3-4]. Recently, a MUX-based binary INC/DEC which is more efficient than the previous INC/DECs has been proposed in literature [5]. A gray INC/DEC (same as a gray code counter) consists of a binary INC/DEC coupled with gray to binary and binary to gray converters [6]. Since there is only one bit difference between adjacent numbers in a gray code sequence, only one bit transitions occur while counting with gray incrementer/decrementer. This limits the potential for transition errors as well as reduces the electrical noise generated unlike the binary counters. This paper presents novel architectures and implementations for both binary and gray INC/DECs. The proposed implementations lay emphasis on the usage of hybrid logic, that is, coupling of transmission gates with CMOS gates at appropriate stages rather than using complete CMOS or transmission gate designs. This reduces high power dissipation due to cascading of transmission gates while giving lesser propagation delay. A novel gray to binary converter is also proposed which is coupled with the binary INC/DEC to obtain a new gray INC/DEC. 2. Binary Incrementer/Decrementers (INC/DECs) 2.1. Existing Architectures for Binary INC/DECs There are various architectures for binary INC/DECs in literature. The carry propagation adder (CPA)-based INC/DEC is shown in Fig. 1(a). In this circuit, in order to implement increment and decrement, the operand B and carry input are tied to the mode selection signal (Inc/Dec) or its complement. With this configuration, there is a carry propagation effect from Cin to Cout through a series of full adders that makes the circuit slow. The carry lookahead adder (CLA) based INC/DEC [7] is shown in Fig. 1(b). Although the speed can be improved to a certain extent, the circuit becomes too complex and has higher power dissipation when compared to CPA-based model. A MUX-based binary INC/DEC, [5] shown in Fig. 1(c), is efficient in terms of both speed and hardware complexity when compared to adder-based INC/DECs. However, a series of (n-1) OR gates in its critical path hampers the speed of the circuit to a certain extent.